velxio/test/test_intel/autosearch/02_intel_chips_overview.md

Per-chip overview (4004, 4040, 8080, 8086, Z80)

These are well-documented chips with public-domain datasheets mirrored in many places (Intel archives, Wikipedia, CPU-world.com, datasheet archives). Numbers below are common-knowledge from the original datasheets; anything I am not sure about is marked [verify].

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Intel 4004 (1971)

• Package: 16-pin DIP.
• Word size: 4-bit.
• Address space: 12 bits → 4 KB program ROM, 1280 nibbles RAM organised across up to 4 banks of 4 chips of 4 registers of 20 characters (data is nibble-addressed, not byte-addressed).
• Bus: Heavily multiplexed. The 4 data pins D0–D3 carry, in successive cycles within an 8-cycle "instruction cycle":
  • A1, A2, A3 — three nibbles of address (12 bits total),
  • M1, M2 — two nibbles of opcode/operand,
  • X1, X2, X3 — three execution sub-cycles.
• Control pins: SYNC (cycle marker), CM-ROM, CM-RAM0..3 (chip-select to ROMs and RAMs), RESET, TEST, CLK1, CLK2 (two-phase clock), VDD, VSS.
• Clock: 740 kHz typical (dual-phase). Instruction cycle = 8 clock phases ≈ 10.8 µs.
• Registers: 16 × 4-bit index registers (R0–R15), 4-bit accumulator, carry, 12-bit program counter, 3-deep PC stack.
• Instruction count: 46 instructions, all 1 or 2 bytes.

Implementation note

The 4004 is the easiest CPU semantically — small ISA, tiny register file — but the most awkward electrically because everything is multiplexed onto 4 pins across an 8-cycle frame. The chip would have to drive SYNC and walk through the A1/A2/A3/M1/M2/X1/X2/X3 phases each instruction.

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Intel 4040 (1974)

• Package: 24-pin DIP.
• Word size: 4-bit.
• Compatibility: Superset of the 4004; same instruction format with additions.
• Additions over 4004:
  • Interrupt input (INT) and interrupt acknowledge.
  • Single-step / STOP / STOP ACK.
  • 8 extra index registers (24 total: R0–R23).
  • PC stack expanded to 7-deep.
  • 14 additional instructions for interrupt and stack handling.
• Bus: Same nibble-multiplexed scheme as 4004 plus the new control signals.
• Clock: 740 kHz, same dual-phase scheme. [verify exact pin-to-pin pinout from a 4040 datasheet before committing the .chip.json]

Implementation note

Reusing the 4004 emulator core and adding the new opcodes + interrupt handling is the obvious path. Most of the new work is the bigger register file and the interrupt vector logic.

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Intel 8080 (1974)

• Package: 40-pin DIP.
• Word size: 8-bit.
• Address bus: 16 bits, separate pins A0–A15 → 64 KB.
• Data bus: 8 bits, separate pins D0–D7. During T1 of each machine cycle the data bus carries a status byte (memory read, I/O write, interrupt acknowledge, etc.); this is normally latched by an external 8228 system controller. We can either model that internally or expose a SYNC/DBIN/WR triplet and let the user wire an 8228-equivalent.
• Control pins: SYNC, DBIN, WR̅, READY, WAIT, HOLD, HLDA, INT, INTE, RESET. Plus power: +12 V, +5 V, −5 V, GND (the real chip needed three rails — we will collapse this to a single VCC/GND pair since velxio is digital).
• Clock: External 2-phase clock, normally generated by an 8224. Typical instruction rate: 2 MHz φ.
• Registers: A, B, C, D, E, H, L (six 8-bit + accumulator), 16-bit SP, 16-bit PC, flags (S, Z, AC, P, CY).
• Instruction count: 244 opcodes (78 base instructions, many register variants).

Implementation note

Cleanest of the bunch electrically — separate address/data buses and a small set of control signals. superzazu/8080 (MIT-licensed single-file C emulator that passes the standard CPUDIAG test) is a strong porting candidate.

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Zilog Z80 (1976)

• Package: 40-pin DIP.
• Word size: 8-bit.
• Compatibility: Binary-compatible with 8080 + extensions.
• Address bus: 16 bits, separate A0–A15.
• Data bus: 8 bits, separate D0–D7.
• Control pins: M1 (opcode fetch marker), MREQ, IORQ, RD, WR, RFSH (DRAM refresh), HALT, WAIT, INT, NMI, RESET, BUSREQ, BUSACK, CLK, +5 V, GND — a single 5 V rail, single clock phase. Much friendlier than the 8080 in this respect.
• Clock: Single-phase. Common rates 2.5 / 4 / 6 / 8 MHz.
• Registers: A, F, B, C, D, E, H, L (main set) + identical shadow set (A', F', …); IX, IY (16-bit index); SP, PC; I (interrupt vector); R (memory refresh, 7-bit increments each M1).
• Interrupt modes: IM0, IM1 (RST 38h), IM2 (vectored via I).
• Instruction count: ~700 effective opcodes including CB, ED, DD, FD, DDCB, FDCB prefix tables.

Implementation note

The Z80 is the best documented of the lot: Andre Weissflog's floooh/chips/z80.h is a single-header MIT-licensed cycle-accurate emulator. Porting it as-is (or close to as-is) into a velxio chip is the most credible "first instruction-level CPU" milestone.

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Intel 8086 (1978)

• Package: 40-pin DIP.
• Word size: 16-bit.
• Address bus: 20 bits → 1 MB (with segment:offset addressing, segments are 16-bit shifted left 4 = 64 KB windows in 1 MB).
• Data bus: 16-bit, multiplexed with the low 16 address bits on pins AD0–AD15. The high 4 address bits share with status pins A16/S3 .. A19/S6. Demultiplexing is normally done by an 8282/8283 latch driven by ALE.
• Operating modes: Minimum mode (MN/MX̅ tied high) and maximum mode (tied low), which remap several control pins for use with the 8288 bus controller. We will start with minimum mode.
• Control pins (min mode): ALE, RD, WR, M/IO, DT/R, DEN, HOLD, HLDA, INTR, NMI, INTA, TEST, READY, RESET, CLK. Plus the multiplexed AD bus.
• Clock: External, generated by 8284A. Rates: 5, 8, 10 MHz.
• Registers: AX/BX/CX/DX (each split into high/low), SP, BP, SI, DI; CS, DS, SS, ES segment registers; IP; flags.
• Instruction set: Variable-length 1–6 byte instructions. Prefetch queue (6 bytes on 8086, 4 on 8088) — emulators usually skip micro-architectural prefetch and just decode at IP, which is fine for most software.

Implementation note

The 8086 is the most ambitious target. The killer features versus the 8080/Z80:

• AD bus multiplexing — the chip has to drive ALE to latch addresses and then either drive or read 16 data bits in the same pin group.
• 20-bit physical addresses from 16-bit segment + 16-bit offset.
• Variable-length decode and a much bigger ISA (effective addressing modes, ModR/M byte).

Adrian Cable's 8086tiny (~4 KB of dense C, MIT-style) is the canonical small-footprint 8086 emulator and a credible porting source. License needs review before vendoring into the repo.

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Pin-count budget summary

Chip	Real pin count	Pins we need to register in velxio
4004	16	16 (or fewer if we collapse the two unused VDD/VSS)
4040	24	24
8080	40	~38 (collapse the 3 power rails into one VCC)
Z80	40	40
8086	40	40

All within the runtime's per-chip pin table. Nothing here is a blocker.