test_intel: phase E — 8086 ISA expansion
Adds ~600 LOC to 8086.c bringing the chip from ~50 opcodes to a
near-complete subset of the iAPX 86 ISA:
- Shift/rotate Group 2 (D0..D3) — ROL/ROR/RCL/RCR/SHL/SHR/SAR with
imm-1 or CL count, full CF + OF + S/Z/P semantics.
- String ops MOVS/CMPS/SCAS/LODS/STOS (byte + word) with REP/REPE/
REPNE prefix loop; DF-respecting SI/DI advance.
- MUL/IMUL/DIV/IDIV (Group 3 sub-opcodes 4-7) with divide-error halt.
- BCD: DAA/DAS/AAA/AAS/AAM/AAD with manual-canonical algorithms.
- Port I/O: IN/OUT byte+word, immediate or DX-indexed.
- Hardware interrupts: NMI rising → vector 2, INTR + IF → INTA cycle
reading vector byte from data bus, INT imm8/3, INTO, IRET.
- LDS/LES, LAHF/SAHF, XCHG byte+word, XLAT.
- Group 4 (FE) INC/DEC r/m8 (was missing).
- PUSH/POP segment regs (06/0E/16/1E + 07/17/1F).
- Undocumented: POP CS (0F), SALC (D6).
- TEST r/m,r and TEST AL/AX,imm (84/85/A8/A9 — also missing baseline).
New harness:
- BoardHarness.installFake8086Bus() — full 8086 minimum-mode bus
responder: ALE-snapshot + RD-drive + WR-latch.
- boot8086() helper in 8086.test.js placing test bytes at physical
0xF0100 with reset-vector JMP-FAR stub.
Tests: 8086 3→10 passing (+7: MOV imm16, ADD, JMP near, SHL, MUL,
REP MOVSB, segment override). Total test_intel: 86→93 passing,
0 failed, 12 todo.
CALL/RET test deferred to it.todo — chip takes an unintended path
after the CALL push (debug ongoing). Master plan doc updated.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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