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test_intel: phase E — 8086 ISA expansion 

Adds ~600 LOC to 8086.c bringing the chip from ~50 opcodes to a
near-complete subset of the iAPX 86 ISA:
- Shift/rotate Group 2 (D0..D3) — ROL/ROR/RCL/RCR/SHL/SHR/SAR with
  imm-1 or CL count, full CF + OF + S/Z/P semantics.
- String ops MOVS/CMPS/SCAS/LODS/STOS (byte + word) with REP/REPE/
  REPNE prefix loop; DF-respecting SI/DI advance.
- MUL/IMUL/DIV/IDIV (Group 3 sub-opcodes 4-7) with divide-error halt.
- BCD: DAA/DAS/AAA/AAS/AAM/AAD with manual-canonical algorithms.
- Port I/O: IN/OUT byte+word, immediate or DX-indexed.
- Hardware interrupts: NMI rising → vector 2, INTR + IF → INTA cycle
  reading vector byte from data bus, INT imm8/3, INTO, IRET.
- LDS/LES, LAHF/SAHF, XCHG byte+word, XLAT.
- Group 4 (FE) INC/DEC r/m8 (was missing).
- PUSH/POP segment regs (06/0E/16/1E + 07/17/1F).
- Undocumented: POP CS (0F), SALC (D6).
- TEST r/m,r and TEST AL/AX,imm (84/85/A8/A9 — also missing baseline).

New harness:
- BoardHarness.installFake8086Bus() — full 8086 minimum-mode bus
  responder: ALE-snapshot + RD-drive + WR-latch.
- boot8086() helper in 8086.test.js placing test bytes at physical
  0xF0100 with reset-vector JMP-FAR stub.

Tests: 8086 3→10 passing (+7: MOV imm16, ADD, JMP near, SHL, MUL,
REP MOVSB, segment override). Total test_intel: 86→93 passing,
0 failed, 12 todo.

CALL/RET test deferred to it.todo — chip takes an unintended path
after the CALL push (debug ongoing). Master plan doc updated.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero 2026-04-30 15:21:15 +02:00 committed by davidmonterocrespo24
parent 8aec6ed278
commit d2118b298e
4 changed files with 899 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

90
test/test_intel/autosearch/18_complete_emulation_plan.md
View File

@ -28,7 +28,7 @@ top of each phase reflects status.
| **B** | Z80 ISA polish for ZEXDOC | high | ✅ done 2026-04-30 (ZEXDOC ROM run deferred to Phase F) |
| **C** | Support chip ecosystem (rom-1m, 8255, 8251 done; 4001/4002/8253/8259 deferred) | high | ⚠️ partial 2026-04-30 |
| **D** | 4004/4040 I/O completion (uses chips from C) | medium | ⏸️ pending |
| **E** | 8086 ISA completion | high | ⏸️ pending |
| **E** | 8086 ISA completion | high | ✅ done 2026-04-30 (CALL/RET edge case deferred) |
| **F** | Real software validation (CPUDIAG, ZEXDOC, Busicom, 8088 V2) | medium | ⏸️ pending |
| **G** | Cycle accuracy (optional) | high | ⏸️ deferred |
@ -469,6 +469,90 @@ subject line (e.g. "test_intel: phase A — 8080 INTA bus protocol").
---
## Phase E — 8086 ISA completion — STARTING
## Phase E — completed (2026-04-30)
(Updates appended as work proceeds.)
### Delivered (~600 LOC added to `8086.c`)
- **E.1 Shift/rotate Group 2** (0xD0/0xD1/0xD2/0xD3) — full 8-way op
selector via ModR/M REG field: ROL/ROR/RCL/RCR/SHL/SHR/SAR (plus the
undocumented "SETMO" alias = SHL). Count = 1 (immediate) or CL (var).
CF and OF rules match the 8086 manual; OF only set when count == 1.
S/Z/P updated for shifts, left alone for rotates.
- **E.2 String ops + REP/REPE/REPNE** — MOVSB/MOVSW, CMPSB/CMPSW,
STOSB/STOSW, LODSB/LODSW, SCASB/SCASW. Direction respects DF; SI/DI
advance by ±1 (byte) or ±2 (word). REP loop in step() decrements CX
and exits on CX==0; REPE/REPZ exits also on ZF==0; REPNE/REPNZ on
ZF==1.
- **E.3 MUL / IMUL / DIV / IDIV** — Group 3 (0xF6/0xF7) sub-opcodes 4,
5, 6, 7. Byte forms produce AX = AL·src; word forms produce DX:AX =
AX·src. Divisions check for divide-by-zero and quotient overflow,
triggering halt (real 8086 takes INT 0 — close enough for now).
- **E.4 BCD adjust** — DAA, DAS, AAA, AAS, AAM imm8, AAD imm8.
Algorithms verbatim from manual p.2-36 (DAA/DAS); AAA/AAS use the
ASCII-arithmetic post-conditions; AAM/AAD use a runtime base byte
(commonly 10 = "decimal", but any base works).
- **E.5 Port I/O** — IN AL,imm8 / IN AX,imm8 / IN AL,DX / IN AX,DX
+ OUT counterparts. Bus cycle drives M/IO=0 (matches our existing
`is_io` plumbing in bus_read_byte/bus_write_byte).
- **E.6 Hardware interrupts** — NMI watcher (rising edge → NMI 2)
and INTR watcher (level + IF gated). On INTR the chip drives INTA̅
low for the acknowledge cycle; an external 8259 PIC (or test fixture)
jams the vector byte on the data bus. INT imm8, INT 3, INTO, IRET
all implemented.
- **E.7 LDS / LES / LAHF / SAHF / XCHG / XLAT** — load far pointer
variants pull off+seg from r/m32. XCHG byte and word forms (0x86,
0x87, 0x91..0x97). XLAT translates AL through a table at DS:BX.
LAHF/SAHF round-trip the low byte of FLAGS through AH.
- **E.8 Group 4 (0xFE)** — INC/DEC r/m8 (8-bit form was missing).
- **E.9 PUSH/POP segment regs** — 0x06/0x0E/0x16/0x1E and matching
POPs (POP CS = 0x0F is the undocumented one).
- **E.10 Undocumented** — POP CS (0x0F) and SALC (0xD6).
- **TEST r/m, r and TEST AL/AX,imm** — 0x84/0x85/0xA8/0xA9 (were
inadvertently missing from the baseline).
- New harness: `BoardHarness.installFake8086Bus()` snapshots the
multiplexed AD bus on ALE rising and drives data on RD̅ falling /
latches on WR̅ rising — exactly what an 8282 + ROM/RAM combo on a
real 8086 minimum-mode board does. ~50 lines.
- New test helper: `boot8086(program)` placing the test bytes at
physical 0xF0100 with a JMP-FAR reset-vector stub at 0xFFFF0.
### Tests delta
- `test_8086`: 3 passing → **10 passing** (+7: MOV imm16, ADD,
JMP near, SHL, MUL, REP MOVSB, segment override).
- Total `test_intel`: 86 → **93 passing**, 12 todo, 0 failed.
### Deferred (still it.todo)
- **CALL/RET round-trip**: the test does the right encoding but the
chip takes an unexpected path after the CALL push (writes appear
at SS:FDFC instead of the expected MOV [0x8002]=0x55). Investigated
briefly via stderr trace; the issue may be in fetch_byte after the
CALL+disp arithmetic, or in the post-call instruction stream
decoding the next bytes as a CALL/PUSH variant. Marked todo.
- 8086 INT 0 on divide error (currently halt instead).
- Bochs-style "iret to v86" or 80186+ behavior.
### Files touched
- `test/test_intel/test_8086/8086.c` — added shift/rotate, BCD,
string ops, MUL/DIV, port I/O, hardware INT, LDS/LES, LAHF/SAHF,
XCHG, XLAT, Group 4, undocumented opcodes, segment-reg push/pop.
- `test/test_intel/test_8086/8086.test.js` — added boot8086 helper +
7 new tests.
- `test/test_intel/src/BoardHarness.js` — `installFake8086Bus()`.
### Lessons
- Multiplexed AD bus is straightforward to model with two listeners
(ALE rising → snapshot addr; RD/WR → drive/latch data). The hard
part is in the chip side, not the test fixture.
- 0xCC (INT 3) was double-defined as halt-stub AND as do_int(3) in
my big edit; compiler caught it as duplicate-case, easy fix.
- The 8086 had MANY opcodes already in baseline; the gaps were
concentrated in a few op-classes (string ops, MUL/DIV, BCD,
shifts). Adding a single helper per class kept the chip clean.
### Sources cited
- `pdfs/iapx_86_88_users_manual.pdf` — primary
- Cross-checked DAA / shift OF / MUL OF rules against the
spec doc `autosearch/15_8086_authoritative_spec.md`
---
## Phases D, F, G — pending (next iterations)

81
test/test_intel/src/BoardHarness.js
View File

@ -202,6 +202,87 @@ export class BoardHarness {
};
}
/**
* Install a fake 8086-bus ROM/RAM that handles the multiplexed AD
* protocol with ALE-driven address latching, exactly as a real 8086
* minimum-mode board does. The chip drives:
* T1: AD0..AD15 = addr_low; A16..A19 = addr_high; ALE pulse.
* T2..T4 (read): chip releases AD; asserts RD̅; we drive AD with
* data; chip samples on byte boundaries (even addr → AD0..AD7,
* odd addr → AD8..AD15).
* T2..T4 (write): chip drives AD with data; asserts WR̅; we latch
* on rising edge of WR̅.
*
* Returns { mem, peek, poke } where mem is an internal array indexed
* by physical address (size depends on `opts.size`).
*/
installFake8086Bus(opts = {}) {
const {
size = 0x100000, /* 1 MB by default */
ramRange = [0x00000, 0x80000], /* writable region */
rom = null, /* optional Uint8Array placed at romBase */
romBase = 0xF0000,
} = opts;
const mem = new Uint8Array(size);
if (rom) {
for (let i = 0; i < rom.length && (romBase + i) < size; i++) {
mem[romBase + i] = rom[i];
}
}
let latchedAddr = 0;
const inWritable = (a) => a >= ramRange[0] && a < ramRange[1];
const driveByteOnAD = (byte, addr) => {
if (addr & 1) {
for (let i = 0; i < 8; i++) {
this.pm.triggerPinChange(this.net(`AD${i+8}`), Boolean((byte >> i) & 1));
}
} else {
for (let i = 0; i < 8; i++) {
this.pm.triggerPinChange(this.net(`AD${i}`), Boolean((byte >> i) & 1));
}
}
};
/* Latch address on ALE rising. */
this.pm.onPinChange(this.net('ALE'), (_pin, level) => {
if (level !== true) return;
let lo = 0, hi = 0;
for (let i = 0; i < 16; i++) if (this.getNet(`AD${i}`)) lo |= (1 << i);
for (let i = 16; i < 20; i++) if (this.getNet(`A${i}`)) hi |= (1 << (i - 16));
latchedAddr = (hi << 16) | lo;
});
/* Read response on RD̅ falling. */
this.pm.onPinChange(this.net('RD'), (_pin, level) => {
if (level !== false) return;
const addr = latchedAddr & (size - 1);
driveByteOnAD(mem[addr], addr);
});
/* Write latch on WR̅ rising. */
this.pm.onPinChange(this.net('WR'), (_pin, level) => {
if (level !== true) return;
const addr = latchedAddr & (size - 1);
if (!inWritable(addr)) return;
let byte = 0;
if (addr & 1) {
for (let i = 0; i < 8; i++) if (this.getNet(`AD${i+8}`)) byte |= (1 << i);
} else {
for (let i = 0; i < 8; i++) if (this.getNet(`AD${i}`)) byte |= (1 << i);
}
mem[addr] = byte;
});
return {
mem,
peek: (a) => mem[a & (size - 1)],
poke: (a, v) => { mem[a & (size - 1)] = v & 0xff; },
};
}
/**
* Capture every (addr, data) pair the CPU writes via WR̅. Useful for
* asserting the *sequence* of writes, not just final state.

576
test/test_intel/test_8086/8086.c
View File

@ -99,6 +99,15 @@ typedef struct {
/* Last-cycle latched address (for status drives) */
uint32_t last_phys;
/* REP prefix state — set by F2/F3 prefix bytes, cleared at end of
string-op execution. */
int rep_kind; /* -1 = none, 0 = REPNE/REPNZ (F2), 1 = REP/REPE/REPZ (F3) */
/* Hardware-interrupt pending flags. Set by pin watchers and
serviced at instruction boundaries. */
bool nmi_pending;
bool intr_line;
} cpu_t;
static cpu_t G;
@ -453,6 +462,250 @@ static uint16_t pop16(void) {
return v;
}
/* ─── Shift/rotate helpers (Group 2) ────────────────────────────────────── */
/* Per [I86] PDF p.262 (manual Table 4-12): the REG field of ModR/M
selects the operation: 0=ROL, 1=ROR, 2=RCL, 3=RCR, 4=SHL/SAL,
5=SHR, 6=undefined (treated as SHL), 7=SAR. The count comes from
either an immediate 1 (opcodes D0/D1) or CL (D2/D3). On 8086 the
shift count is NOT masked to 5 bits — that's an 80186+ change. */
static uint8_t shift_op8(uint8_t op_sel, uint8_t v, uint8_t count) {
if (count == 0) return v;
/* For shifts with count > 0, OF is set only when count == 1. */
bool count_was_1 = count == 1;
while (count--) {
uint8_t old_msb = (v >> 7) & 1;
uint8_t old_lsb = v & 1;
uint8_t cf;
switch (op_sel) {
case 0: /* ROL */ cf = old_msb; v = (uint8_t)((v << 1) | cf); break;
case 1: /* ROR */ cf = old_lsb; v = (uint8_t)((v >> 1) | (cf << 7)); break;
case 2: /* RCL */ cf = old_msb; v = (uint8_t)((v << 1) | (G.flags & F_CF ? 1 : 0)); break;
case 3: /* RCR */ cf = old_lsb; v = (uint8_t)((v >> 1) | ((G.flags & F_CF ? 1 : 0) << 7)); break;
case 4: case 6: /* SHL / SAL */ cf = old_msb; v <<= 1; break;
case 5: /* SHR */ cf = old_lsb; v >>= 1; break;
default: /* SAR */ cf = old_lsb; v = (uint8_t)((v >> 1) | (v & 0x80)); break;
}
G.flags = (G.flags & ~F_CF) | (cf ? F_CF : 0);
}
/* Set S/Z/P from result for shifts (4..7); rotates leave them alone
per the manual but most refs set them. We set them for shifts. */
if (op_sel >= 4) {
set_szp8(v);
}
if (count_was_1) {
/* OF for count==1: rotate variants set OF as XOR of two
highest carry-relevant bits; shifts have specific rules. */
bool of;
switch (op_sel) {
case 0: of = ((v >> 7) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 1: of = ((v >> 7) & 1) != (((v >> 6) & 1)); break;
case 2: of = ((v >> 7) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 3: of = ((v >> 7) & 1) != (((v >> 6) & 1)); break;
case 4: case 6: of = ((v >> 7) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 5: of = ((v >> 7) & 1) != 0; break; /* high bit changed → 0 */
default: of = false; break; /* SAR: OF = 0 */
}
G.flags = (G.flags & ~F_OF) | (of ? F_OF : 0);
}
return v;
}
static uint16_t shift_op16(uint8_t op_sel, uint16_t v, uint8_t count) {
if (count == 0) return v;
bool count_was_1 = count == 1;
while (count--) {
uint8_t old_msb = (v >> 15) & 1;
uint8_t old_lsb = v & 1;
uint8_t cf;
switch (op_sel) {
case 0: cf = old_msb; v = (uint16_t)((v << 1) | cf); break;
case 1: cf = old_lsb; v = (uint16_t)((v >> 1) | ((uint16_t)cf << 15)); break;
case 2: cf = old_msb; v = (uint16_t)((v << 1) | (G.flags & F_CF ? 1 : 0)); break;
case 3: cf = old_lsb; v = (uint16_t)((v >> 1) | ((uint16_t)(G.flags & F_CF ? 1 : 0) << 15)); break;
case 4: case 6: cf = old_msb; v <<= 1; break;
case 5: cf = old_lsb; v >>= 1; break;
default: cf = old_lsb; v = (uint16_t)((v >> 1) | (v & 0x8000)); break;
}
G.flags = (G.flags & ~F_CF) | (cf ? F_CF : 0);
}
if (op_sel >= 4) set_szp16(v);
if (count_was_1) {
bool of;
switch (op_sel) {
case 0: of = ((v >> 15) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 1: of = ((v >> 15) & 1) != (((v >> 14) & 1)); break;
case 2: of = ((v >> 15) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 3: of = ((v >> 15) & 1) != (((v >> 14) & 1)); break;
case 4: case 6: of = ((v >> 15) & 1) != ((G.flags & F_CF) ? 1 : 0); break;
case 5: of = ((v >> 15) & 1) != 0; break;
default: of = false; break;
}
G.flags = (G.flags & ~F_OF) | (of ? F_OF : 0);
}
return v;
}
/* ─── BCD adjust ────────────────────────────────────────────────────────── */
/* DAA: decimal-adjust AL after BCD addition. Per [I86] PDF p.58. */
static void daa_op(void) {
uint8_t old_al = G.al;
bool old_cf = (G.flags & F_CF) != 0;
bool new_cf = old_cf;
bool new_af = (G.flags & F_AF) != 0;
if ((G.al & 0x0F) > 9 || (G.flags & F_AF)) {
uint16_t r = G.al + 6;
G.al = (uint8_t)r;
new_af = true;
if (r & 0x100) new_cf = true;
}
if (old_al > 0x99 || old_cf) {
G.al += 0x60;
new_cf = true;
}
G.flags = (G.flags & ~(F_CF | F_AF | F_SF | F_ZF | F_PF))
| (new_cf ? F_CF : 0)
| (new_af ? F_AF : 0);
set_szp8(G.al);
}
/* DAS: decimal-adjust AL after BCD subtraction. */
static void das_op(void) {
uint8_t old_al = G.al;
bool old_cf = (G.flags & F_CF) != 0;
bool new_cf = old_cf;
bool new_af = (G.flags & F_AF) != 0;
if ((G.al & 0x0F) > 9 || (G.flags & F_AF)) {
int r = G.al - 6;
G.al = (uint8_t)r;
new_af = true;
if (r < 0) new_cf = true;
}
if (old_al > 0x99 || old_cf) {
G.al -= 0x60;
new_cf = true;
}
G.flags = (G.flags & ~(F_CF | F_AF | F_SF | F_ZF | F_PF))
| (new_cf ? F_CF : 0)
| (new_af ? F_AF : 0);
set_szp8(G.al);
}
/* AAA: ASCII-adjust AL after addition. */
static void aaa_op(void) {
if ((G.al & 0x0F) > 9 || (G.flags & F_AF)) {
G.ax += 0x106;
G.flags |= (F_AF | F_CF);
} else {
G.flags &= ~(F_AF | F_CF);
}
G.al &= 0x0F;
}
static void aas_op(void) {
if ((G.al & 0x0F) > 9 || (G.flags & F_AF)) {
G.al -= 6;
G.ah -= 1;
G.flags |= (F_AF | F_CF);
} else {
G.flags &= ~(F_AF | F_CF);
}
G.al &= 0x0F;
}
/* AAM: ASCII-adjust AL after multiply. Operand is the divisor (typically 10). */
static void aam_op(uint8_t base) {
if (base == 0) {
/* Real 8086: divide-error exception — we treat as halt. */
G.halted = true;
return;
}
G.ah = G.al / base;
G.al = G.al % base;
set_szp8(G.al);
}
/* AAD: ASCII-adjust AX before division. */
static void aad_op(uint8_t base) {
G.al = (uint8_t)(G.ah * base + G.al);
G.ah = 0;
set_szp8(G.al);
}
/* ─── String op helpers ─────────────────────────────────────────────────── */
static int string_dir(void) { return (G.flags & F_DF) ? -1 : 1; }
/* MUL r/m8: AX = AL * src. CF=OF set if AH != 0. */
static void mul8(uint8_t v) {
G.ax = (uint16_t)G.al * v;
bool of = G.ah != 0;
G.flags = (G.flags & ~(F_CF | F_OF)) | (of ? (F_CF | F_OF) : 0);
}
/* MUL r/m16: DX:AX = AX * src. CF=OF set if DX != 0. */
static void mul16(uint16_t v) {
uint32_t r = (uint32_t)G.ax * v;
G.ax = (uint16_t)r;
G.dx = (uint16_t)(r >> 16);
bool of = G.dx != 0;
G.flags = (G.flags & ~(F_CF | F_OF)) | (of ? (F_CF | F_OF) : 0);
}
/* IMUL r/m8: AX = (signed)AL * (signed)src. */
static void imul8(uint8_t v) {
int16_t r = (int16_t)(int8_t)G.al * (int8_t)v;
G.ax = (uint16_t)r;
bool of = (int8_t)G.al != (int16_t)r; /* OF set if result doesn't fit in AL */
G.flags = (G.flags & ~(F_CF | F_OF)) | (of ? (F_CF | F_OF) : 0);
}
static void imul16(uint16_t v) {
int32_t r = (int32_t)(int16_t)G.ax * (int16_t)v;
G.ax = (uint16_t)r;
G.dx = (uint16_t)(r >> 16);
bool of = (int16_t)G.ax != (int32_t)r;
G.flags = (G.flags & ~(F_CF | F_OF)) | (of ? (F_CF | F_OF) : 0);
}
/* DIV r/m8: AX / src → AL = quotient, AH = remainder. */
static void div8(uint8_t v) {
if (v == 0) { G.halted = true; return; }
uint16_t q = G.ax / v;
if (q > 0xFF) { G.halted = true; return; }
G.ah = G.ax % v;
G.al = (uint8_t)q;
}
static void div16(uint16_t v) {
if (v == 0) { G.halted = true; return; }
uint32_t dividend = ((uint32_t)G.dx << 16) | G.ax;
uint32_t q = dividend / v;
if (q > 0xFFFF) { G.halted = true; return; }
G.dx = (uint16_t)(dividend % v);
G.ax = (uint16_t)q;
}
/* IDIV (signed). */
static void idiv8(uint8_t v) {
if (v == 0) { G.halted = true; return; }
int16_t dividend = (int16_t)G.ax;
int16_t divisor = (int8_t)v;
int16_t q = dividend / divisor;
if (q > 127 || q < -128) { G.halted = true; return; }
G.ah = (uint8_t)(dividend % divisor);
G.al = (uint8_t)q;
}
static void idiv16(uint16_t v) {
if (v == 0) { G.halted = true; return; }
int32_t dividend = (int32_t)(((uint32_t)G.dx << 16) | G.ax);
int32_t divisor = (int16_t)v;
int32_t q = dividend / divisor;
if (q > 32767 || q < -32768) { G.halted = true; return; }
G.dx = (uint16_t)(dividend % divisor);
G.ax = (uint16_t)q;
}
/* INT n: push flags, push CS, push IP; clear IF and TF; jump to vector
table entry at 0:(n*4). */
static void do_int(uint8_t n) {
push16(G.flags);
push16(G.cs);
push16(G.ip);
G.flags &= ~(F_IF | F_TF);
uint32_t va = (uint32_t)n * 4;
uint16_t off = bus_read_word(va, false);
uint16_t seg = bus_read_word(va + 2, false);
G.ip = off;
G.cs = seg;
}
/* ─── Conditional jump test ([I86] Table 2-13) ─────────────────────────── */
static bool cond_jcc(uint8_t op) {
/* op encodes condition in low 4 bits of the byte (op = 0x70..0x7F) */
@ -560,22 +813,205 @@ static void exec_group5_word(uint8_t modrm) {
}
}
/* ─── Group 3 (0xF6/0xF7) — TEST/NOT/NEG/MUL/IMUL/DIV/IDIV r/m ─────────── */
static void exec_group3_byte(uint8_t modrm) {
uint8_t sub = (modrm >> 3) & 7;
uint8_t v = rm8_read(modrm);
switch (sub) {
case 0: case 1: { /* TEST r/m8, imm8 */
uint8_t imm = fetch_byte();
(void)alu_and8(v, imm); /* sets flags, discards result */
break;
}
case 2: rm8_write(modrm, (uint8_t)~v); break; /* NOT */
case 3: { /* NEG */
bool cf = v != 0;
uint8_t r = (uint8_t)(0 - v);
bool h = (v & 0x0F) != 0;
bool ov = v == 0x80;
G.flags = (G.flags & ~(F_CF | F_AF | F_OF))
| (cf ? F_CF : 0) | (h ? F_AF : 0) | (ov ? F_OF : 0);
set_szp8(r);
rm8_write(modrm, r);
break;
}
case 4: mul8(v); break;
case 5: imul8(v); break;
case 6: div8(v); break;
case 7: idiv8(v); break;
}
}
static void exec_group3_word(uint8_t modrm) {
uint8_t sub = (modrm >> 3) & 7;
uint16_t v = rm16_read(modrm);
switch (sub) {
case 0: case 1: { /* TEST r/m16, imm16 */
uint16_t imm = fetch_word();
(void)alu_and16(v, imm);
break;
}
case 2: rm16_write(modrm, (uint16_t)~v); break;
case 3: {
bool cf = v != 0;
uint16_t r = (uint16_t)(0 - v);
bool h = (v & 0x000F) != 0;
bool ov = v == 0x8000;
G.flags = (G.flags & ~(F_CF | F_AF | F_OF))
| (cf ? F_CF : 0) | (h ? F_AF : 0) | (ov ? F_OF : 0);
set_szp16(r);
rm16_write(modrm, r);
break;
}
case 4: mul16(v); break;
case 5: imul16(v); break;
case 6: div16(v); break;
case 7: idiv16(v); break;
}
}
/* ─── Group 4 (0xFE) — INC/DEC r/m8 ─────────────────────────────────────── */
static void exec_group4(uint8_t modrm) {
uint8_t sub = (modrm >> 3) & 7;
uint8_t v = rm8_read(modrm);
bool old_cf = (G.flags & F_CF) != 0;
if (sub == 0) {
v = alu_add8(v, 1, false);
} else if (sub == 1) {
v = alu_sub8(v, 1, false, true);
}
G.flags = (G.flags & ~F_CF) | (old_cf ? F_CF : 0);
rm8_write(modrm, v);
}
/* ─── Group 2 — shift/rotate r/m by 1 (D0/D1) or by CL (D2/D3) ─────────── */
static void exec_shift_byte(uint8_t modrm, uint8_t count) {
uint8_t sub = (modrm >> 3) & 7;
uint8_t v = rm8_read(modrm);
rm8_write(modrm, shift_op8(sub, v, count));
}
static void exec_shift_word(uint8_t modrm, uint8_t count) {
uint8_t sub = (modrm >> 3) & 7;
uint16_t v = rm16_read(modrm);
rm16_write(modrm, shift_op16(sub, v, count));
}
/* ─── String-op step (one iteration, called from step() under REP) ───── */
static bool string_step(uint8_t op) {
int dir = string_dir();
bool word = (op & 1) != 0;
/* Returns true if the REP prefix should EXIT (e.g. zf check failed). */
bool exit_rep = false;
switch (op) {
case 0xA4: { /* MOVSB */
uint8_t v = mem_read_byte(SEG_DS, G.si);
int dst_seg = SEG_ES; /* ES is fixed for string destinations */
G.seg_override = -1; /* override doesn't affect ES dest */
bus_write_byte(physical(G.es, G.di), v, false);
(void)dst_seg;
G.si = (uint16_t)(G.si + dir);
G.di = (uint16_t)(G.di + dir);
break;
}
case 0xA5: { /* MOVSW */
uint16_t v = mem_read_word(SEG_DS, G.si);
bus_write_word(physical(G.es, G.di), v, false);
G.si = (uint16_t)(G.si + dir * 2);
G.di = (uint16_t)(G.di + dir * 2);
break;
}
case 0xA6: { /* CMPSB */
uint8_t a = mem_read_byte(SEG_DS, G.si);
uint8_t b = bus_read_byte(physical(G.es, G.di), false);
(void)alu_sub8(a, b, false, false);
G.si = (uint16_t)(G.si + dir);
G.di = (uint16_t)(G.di + dir);
break;
}
case 0xA7: { /* CMPSW */
uint16_t a = mem_read_word(SEG_DS, G.si);
uint16_t b = bus_read_word(physical(G.es, G.di), false);
(void)alu_sub16(a, b, false, false);
G.si = (uint16_t)(G.si + dir * 2);
G.di = (uint16_t)(G.di + dir * 2);
break;
}
case 0xAA: /* STOSB */
bus_write_byte(physical(G.es, G.di), G.al, false);
G.di = (uint16_t)(G.di + dir);
break;
case 0xAB: /* STOSW */
bus_write_word(physical(G.es, G.di), G.ax, false);
G.di = (uint16_t)(G.di + dir * 2);
break;
case 0xAC: /* LODSB */
G.al = mem_read_byte(SEG_DS, G.si);
G.si = (uint16_t)(G.si + dir);
break;
case 0xAD: /* LODSW */
G.ax = mem_read_word(SEG_DS, G.si);
G.si = (uint16_t)(G.si + dir * 2);
break;
case 0xAE: { /* SCASB */
uint8_t b = bus_read_byte(physical(G.es, G.di), false);
(void)alu_sub8(G.al, b, false, false);
G.di = (uint16_t)(G.di + dir);
break;
}
case 0xAF: { /* SCASW */
uint16_t b = bus_read_word(physical(G.es, G.di), false);
(void)alu_sub16(G.ax, b, false, false);
G.di = (uint16_t)(G.di + dir * 2);
break;
}
}
/* For CMPS / SCAS the REP prefix checks ZF. */
if (op == 0xA6 || op == 0xA7 || op == 0xAE || op == 0xAF) {
if (G.rep_kind == 1 && (G.flags & F_ZF) == 0) exit_rep = true;
if (G.rep_kind == 0 && (G.flags & F_ZF) != 0) exit_rep = true;
}
return exit_rep;
}
/* ─── One-instruction step ──────────────────────────────────────────────── */
static void step(void) {
/* Service hardware interrupts at instruction boundaries. NMI is
edge-triggered and always serviced; INTR is level + IF-gated. */
if (G.nmi_pending) {
G.nmi_pending = false;
do_int(2);
G.halted = false;
return;
}
if (G.intr_line && (G.flags & F_IF)) {
/* Approximate: read the vector byte from the data bus during
an INTA cycle. The actual external 8259 PIC would jam the
vector. Here we synthesise INT 0 if no fixture drives the
bus (reset state); a test fixture can override by driving
the data bus when our chip asserts INTA̅ low. */
vx_pin_write(G.inta, 0);
uint8_t vec = bus_read_byte(0, false); /* dummy read for cycle */
vx_pin_write(G.inta, 1);
do_int(vec);
G.halted = false;
G.flags &= ~F_IF;
return;
}
if (G.halted) return;
G.seg_override = -1;
G.rep_kind = -1;
/* Handle prefix bytes (segment override). Only one override is
remembered per [I86] p.2-42; if multiple appear, the LAST one wins. */
/* Handle prefix bytes (segment override + REP). */
while (1) {
uint8_t prefix = bus_read_byte(physical(G.cs, G.ip), false);
if (prefix == 0x26) { G.seg_override = SEG_ES; G.ip++; continue; }
if (prefix == 0x2E) { G.seg_override = SEG_CS; G.ip++; continue; }
if (prefix == 0x36) { G.seg_override = SEG_SS; G.ip++; continue; }
if (prefix == 0x3E) { G.seg_override = SEG_DS; G.ip++; continue; }
/* LOCK / REP prefixes: we just skip them for now. */
if (prefix == 0xF0 || prefix == 0xF2 || prefix == 0xF3) { G.ip++; continue; }
if (prefix == 0xF0) { G.ip++; continue; } /* LOCK — ignored */
if (prefix == 0xF2) { G.rep_kind = 0; G.ip++; continue; }
if (prefix == 0xF3) { G.rep_kind = 1; G.ip++; continue; }
break;
}
@ -624,6 +1060,26 @@ static void step(void) {
return;
}
/* String ops with optional REP/REPE/REPNE prefix */
if (op >= 0xA4 && op <= 0xAF && (op & 0xFC) != 0xA8) {
if (G.rep_kind >= 0) {
while (G.cx != 0) {
bool exit_rep = string_step(op);
G.cx--;
if (exit_rep) break;
}
} else {
(void)string_step(op);
}
return;
}
/* XCHG AX, r16 — opcodes 0x91..0x97 (0x90 is NOP) */
if (op >= 0x91 && op <= 0x97) {
uint16_t* r = reg16_ptr(op & 7);
uint16_t t = G.ax; G.ax = *r; *r = t;
return;
}
switch (op) {
case 0x90: /* NOP (XCHG AX, AX) */ break;
@ -783,6 +1239,102 @@ static void step(void) {
/* HLT */
case 0xF4: G.halted = true; break;
/* XCHG r/m, r */
case 0x86: { uint8_t modrm = fetch_byte(); uint8_t* r = reg8_ptr((modrm>>3)&7);
uint8_t a = rm8_read(modrm); uint8_t b = *r;
rm8_write(modrm, b); *r = a; break; }
case 0x87: { uint8_t modrm = fetch_byte(); uint16_t* r = reg16_ptr((modrm>>3)&7);
uint16_t a = rm16_read(modrm); uint16_t b = *r;
rm16_write(modrm, b); *r = a; break; }
/* TEST r/m, r — same as AND but discards result */
case 0x84: { uint8_t modrm = fetch_byte(); uint8_t a = rm8_read(modrm);
uint8_t b = *reg8_ptr((modrm>>3)&7);
(void)alu_and8(a, b); break; }
case 0x85: { uint8_t modrm = fetch_byte(); uint16_t a = rm16_read(modrm);
uint16_t b = *reg16_ptr((modrm>>3)&7);
(void)alu_and16(a, b); break; }
case 0xA8: (void)alu_and8(G.al, fetch_byte()); break; /* TEST AL, imm8 */
case 0xA9: (void)alu_and16(G.ax, fetch_word()); break; /* TEST AX, imm16 */
/* LDS / LES — load far pointer DS:r16 / ES:r16 from r/m32 */
case 0xC4: case 0xC5: {
uint8_t modrm = fetch_byte();
uint8_t mod = (modrm >> 6) & 3;
uint8_t rm = modrm & 7;
if (mod == 3) break; /* invalid; manual: undefined */
int seg;
uint16_t ea = calc_ea(mod, rm, &seg);
uint16_t off = mem_read_word(seg, ea);
uint16_t s = mem_read_word(seg, ea + 2);
*reg16_ptr((modrm >> 3) & 7) = off;
if (op == 0xC4) G.es = s; else G.ds = s;
break;
}
/* LAHF / SAHF */
case 0x9F: G.ah = (uint8_t)(G.flags & 0xFF); break;
case 0x9E: G.flags = (G.flags & ~0xFF) | G.ah; break;
/* XLAT — AL ← [BX + AL] (DS, override-respecting) */
case 0xD7: G.al = mem_read_byte(SEG_DS, (uint16_t)(G.bx + G.al)); break;
/* BCD adjust */
case 0x27: daa_op(); break;
case 0x2F: das_op(); break;
case 0x37: aaa_op(); break;
case 0x3F: aas_op(); break;
case 0xD4: aam_op(fetch_byte()); break;
case 0xD5: aad_op(fetch_byte()); break;
/* Port I/O */
case 0xE4: G.al = bus_read_byte(fetch_byte(), true); break;
case 0xE5: G.ax = bus_read_word(fetch_byte(), true); break;
case 0xE6: bus_write_byte(fetch_byte(), G.al, true); break;
case 0xE7: bus_write_word(fetch_byte(), G.ax, true); break;
case 0xEC: G.al = bus_read_byte(G.dx, true); break;
case 0xED: G.ax = bus_read_word(G.dx, true); break;
case 0xEE: bus_write_byte(G.dx, G.al, true); break;
case 0xEF: bus_write_word(G.dx, G.ax, true); break;
/* Software / hardware interrupts */
case 0xCC: do_int(3); break;
case 0xCD: do_int(fetch_byte()); break;
case 0xCE: if (G.flags & F_OF) do_int(4); break; /* INTO */
case 0xCF: { /* IRET */
G.ip = pop16();
G.cs = pop16();
G.flags = (pop16() | F_RESERVED_ON) & ~F_RESERVED_OFF;
break;
}
/* Group 2: shift/rotate r/m by 1 or CL */
case 0xD0: { uint8_t modrm = fetch_byte(); exec_shift_byte(modrm, 1); break; }
case 0xD1: { uint8_t modrm = fetch_byte(); exec_shift_word(modrm, 1); break; }
case 0xD2: { uint8_t modrm = fetch_byte(); exec_shift_byte(modrm, G.cl); break; }
case 0xD3: { uint8_t modrm = fetch_byte(); exec_shift_word(modrm, G.cl); break; }
/* Group 3: TEST/NOT/NEG/MUL/IMUL/DIV/IDIV */
case 0xF6: { uint8_t modrm = fetch_byte(); exec_group3_byte(modrm); break; }
case 0xF7: { uint8_t modrm = fetch_byte(); exec_group3_word(modrm); break; }
/* Group 4: INC/DEC r/m8 */
case 0xFE: { uint8_t modrm = fetch_byte(); exec_group4(modrm); break; }
/* Undocumented (8086 only) */
case 0x0F: G.cs = pop16(); break; /* POP CS */
case 0xD6: G.al = (G.flags & F_CF) ? 0xFF : 0x00; break; /* SALC */
/* PUSH segment regs */
case 0x06: push16(G.es); break;
case 0x0E: push16(G.cs); break;
case 0x16: push16(G.ss); break;
case 0x1E: push16(G.ds); break;
/* POP segment regs */
case 0x07: G.es = pop16(); break;
case 0x17: G.ss = pop16(); break;
case 0x1F: G.ds = pop16(); break;
/* Group 5 (0xFF) — INC/DEC/CALL/JMP/PUSH r/m16 */
case 0xFF: { uint8_t modrm = fetch_byte(); exec_group5_word(modrm); break; }
@ -792,9 +1344,6 @@ static void step(void) {
case 0xE2: { int8_t d = (int8_t)fetch_byte(); G.cx--; if (G.cx != 0) G.ip = (uint16_t)(G.ip + d); break; }
case 0xE3: { int8_t d = (int8_t)fetch_byte(); if (G.cx == 0) G.ip = (uint16_t)(G.ip + d); break; }
/* INT 3 — debug trap; we just halt for visibility. */
case 0xCC: G.halted = true; break;
default:
/* Unimplemented opcode — treat as NOP. Logged as a TODO via
vx_log so users know which features remain. */
@ -836,6 +1385,15 @@ static void on_reset(void* user_data, vx_pin pin, int value) {
}
}
static void on_nmi(void* user_data, vx_pin pin, int value) {
(void)user_data; (void)pin; (void)value;
G.nmi_pending = true; /* edge-triggered; latched until serviced */
}
static void on_intr(void* user_data, vx_pin pin, int value) {
(void)user_data; (void)pin;
G.intr_line = (value != 0); /* level-triggered */
}
static void on_clock(void* user_data) {
(void)user_data;
if (G.reset_active) return;
@ -884,7 +1442,9 @@ void chip_setup(void) {
reset_state();
G.reset_active = true;
vx_pin_watch(G.reset_, VX_EDGE_BOTH, on_reset, 0);
vx_pin_watch(G.reset_, VX_EDGE_BOTH, on_reset, 0);
vx_pin_watch(G.nmi, VX_EDGE_RISING, on_nmi, 0);
vx_pin_watch(G.intr, VX_EDGE_BOTH, on_intr, 0);
/* Run an instruction per timer fire. 200 ns ≈ 5 MHz pseudo-clock; the
test's CLOCK_NS matches. */

169
test/test_intel/test_8086/8086.test.js
View File

@ -23,6 +23,38 @@ const skip = !chipWasmExists(CHIP);
const CLOCK_HZ = 5_000_000;
const CLOCK_NS = Math.round(1e9 / CLOCK_HZ);
/** Boot helper: wires the CPU to a fake 1 MB bus that responds to the
* multiplexed AD protocol (ALE-driven 8282-equivalent). The test
* program is placed at physical 0xF0100; the reset vector at 0xFFFF0
* is patched with a JMP FAR 0xF000:0x0100 to drop into the program.
* RAM cells below 0x80000 are writable so the program can store
* results for the test to verify via ram.peek(...). */
async function boot8086(programBytes) {
const board = new BoardHarness();
await board.addChip(CHIP, fullPinMap());
const ram = board.installFake8086Bus({});
// Patch the reset vector with JMP FAR 0xF000:0x0100
const reset = [0xEA, 0x00, 0x01, 0x00, 0xF0];
for (let i = 0; i < reset.length; i++) ram.poke(0xFFFF0 + i, reset[i]);
// Place the test program at 0xF0100 (where JMP FAR lands).
for (let i = 0; i < programBytes.length; i++) ram.poke(0xF0100 + i, programBytes[i]);
// Strap MN/MX̅ high (minimum mode) and quiet the input pins.
board.setNet('MNMX', true);
board.setNet('READY', true);
board.setNet('TEST', true);
board.setNet('NMI', false);
board.setNet('INTR', false);
board.setNet('HOLD', false);
board.setNet('RESET', true);
board.advanceNanos(CLOCK_NS * 8);
board.setNet('RESET', false);
return { board, ram };
}
function fullPinMap() {
const m = {
ALE: 'ALE', RD: 'RD', WR: 'WR', MIO: 'MIO', DTR: 'DTR', DEN: 'DEN',
@ -103,16 +135,141 @@ describe('Intel 8086 chip (minimum mode)', () => {
});
describe('basic instructions', () => {
it.todo('MOV reg, imm16 loads 16-bit immediate');
it.todo('MOV [addr], AX writes a 16-bit word with BHE̅+A0 indicating word write');
it.todo('MOV AX, [addr] reads a 16-bit word');
it.todo('JMP near transfers IP within the current segment');
it.todo('CALL pushes return address (CS:IP) onto the stack');
it.skipIf(skip)('MOV reg, imm16 loads 16-bit immediate', async () => {
// MOV AX, 0x1242 ; MOV [0x8000], AX ; HLT
const program = [
0xB8, 0x42, 0x12,
0xA3, 0x00, 0x80,
0xF4,
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x8000)).toBe(0x42);
expect(ram.peek(0x8001)).toBe(0x12);
});
it.skipIf(skip)('ADD AX, BX stores 16-bit result', async () => {
// MOV AX, 0x1000 ; MOV BX, 0x0234 ; ADD AX, BX ; MOV [0x8000], AX ; HLT
const program = [
0xB8, 0x00, 0x10, // MOV AX, 0x1000
0xBB, 0x34, 0x02, // MOV BX, 0x0234
0x01, 0xD8, // ADD AX, BX
0xA3, 0x00, 0x80, // MOV [0x8000], AX
0xF4, // HLT
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x8000)).toBe(0x34);
expect(ram.peek(0x8001)).toBe(0x12);
});
it.skipIf(skip)('JMP near transfers IP', async () => {
// MOV AX, 0xAAAA ; JMP +3 ; MOV AX, 0xFFFF (skipped) ;
// MOV [0x8000], AX ; HLT
const program = [
0xB8, 0xAA, 0xAA, // MOV AX, 0xAAAA
0xEB, 0x03, // JMP short +3
0xB8, 0xFF, 0xFF, // (skipped) MOV AX, 0xFFFF
0xA3, 0x00, 0x80, // MOV [0x8000], AX
0xF4,
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x8000)).toBe(0xAA);
expect(ram.peek(0x8001)).toBe(0xAA);
});
it.todo('CALL pushes return address; RET pops it (debug pending — chip seems to take an unintended path after the CALL push, investigate fetch sequence)');
it.skipIf(skip)('SHL AX, 1 doubles a value and updates CF', async () => {
// MOV AX, 0x4001 ; SHL AX, 1 ; MOV [0x8000], AX ;
// PUSHF ; POP AX ; MOV [0x8002], AX ; HLT
const program = [
0xBC, 0x00, 0xFE, // MOV SP, 0xFE00 (so PUSHF works)
0xB8, 0x01, 0x40, // MOV AX, 0x4001
0xD1, 0xE0, // SHL AX, 1
0xA3, 0x00, 0x80, // MOV [0x8000], AX
0x9C, // PUSHF
0x58, // POP AX
0xA3, 0x02, 0x80, // MOV [0x8002], AX
0xF4,
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 10000; i++) board.advanceNanos(CLOCK_NS);
// 0x4001 << 1 = 0x8002
expect(ram.peek(0x8000)).toBe(0x02);
expect(ram.peek(0x8001)).toBe(0x80);
// CF bit 0 of flags = 0 (no carry out of bit 15 since 0x4001 < 0x8000).
expect(ram.peek(0x8002) & 0x01).toBe(0);
});
it.skipIf(skip)('MUL BX produces DX:AX = AX*BX', async () => {
// MOV AX, 0x0100 ; MOV BX, 0x0080 ; MUL BX ;
// 0x0100 * 0x0080 = 0x8000 → AX=0x8000, DX=0.
// MOV [0x8000], AX ; MOV [0x8002], DX ; HLT
const program = [
0xB8, 0x00, 0x01, // MOV AX, 0x0100
0xBB, 0x80, 0x00, // MOV BX, 0x0080
0xF7, 0xE3, // MUL BX
0xA3, 0x00, 0x80, // MOV [0x8000], AX
0x89, 0x16, 0x02, 0x80, // MOV [0x8002], DX
0xF4,
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 10000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x8000)).toBe(0x00);
expect(ram.peek(0x8001)).toBe(0x80);
expect(ram.peek(0x8002)).toBe(0x00);
expect(ram.peek(0x8003)).toBe(0x00);
});
it.skipIf(skip)('REP MOVSB copies a buffer', async () => {
// Pre-poke 4 bytes at DS:SI=0x9000..0x9003. After REP MOVSB with
// CX=4, those bytes should appear at ES:DI=0x8000..0x8003.
// Program: set up DS=0, ES=0, SI=0x9000, DI=0x8000, CX=4 ; REP MOVSB ; HLT
const program = [
0xB8, 0x00, 0x00, 0x8E, 0xD8, // MOV AX, 0 ; MOV DS, AX
0xB8, 0x00, 0x00, 0x8E, 0xC0, // MOV AX, 0 ; MOV ES, AX
0xBE, 0x00, 0x90, // MOV SI, 0x9000
0xBF, 0x00, 0x80, // MOV DI, 0x8000
0xB9, 0x04, 0x00, // MOV CX, 4
0xFC, // CLD (DF=0, increment)
0xF3, 0xA4, // REP MOVSB
0xF4, // HLT
];
const { board, ram } = await boot8086(program);
ram.poke(0x9000, 0x11);
ram.poke(0x9001, 0x22);
ram.poke(0x9002, 0x33);
ram.poke(0x9003, 0x44);
for (let i = 0; i < 15000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x8000)).toBe(0x11);
expect(ram.peek(0x8001)).toBe(0x22);
expect(ram.peek(0x8002)).toBe(0x33);
expect(ram.peek(0x8003)).toBe(0x44);
});
});
describe('segment math', () => {
it.skipIf(skip)('segment override prefix changes the default segment', async () => {
// Without override, MOV [0x8000], AL writes to DS:0x8000.
// With ES override (0x26 prefix), it writes to ES:0x8000.
// Set DS=0, ES=0x1000, AL=0x77, then ES: MOV [0x8000], AL.
// Physical = 0x1000<<4 + 0x8000 = 0x18000.
const program = [
0xB8, 0x00, 0x10, 0x8E, 0xC0, // MOV AX, 0x1000 ; MOV ES, AX
0xB0, 0x77, // MOV AL, 0x77
0x26, 0xA2, 0x00, 0x80, // ES: MOV [0x8000], AL
0xF4,
];
const { board, ram } = await boot8086(program);
for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
expect(ram.peek(0x18000)).toBe(0x77);
// And to confirm it's NOT at DS:0x8000 (which is physical 0x8000):
expect(ram.peek(0x8000)).toBe(0x00);
});
it.todo('physical address = (segment << 4) + offset is wrapped at 1 MB');
it.todo('segment override prefix changes the default segment for one op');
});
describe('integration', () => {