test_intel: phase D — 4002 RAM chip (basic skeleton)
The 4002 is the data/IO partner of the 4004/4040. 16-pin DIP, 80 nibbles (4 registers × 16 main chars + 4 status chars each), plus 4 dedicated output port pins driven by the WMP instruction. This skeleton: - Pin contract registered (D0..D3, O0..O3, SYNC, CL, RESET, CM, VDD, VSS). - Storage allocated (main[4][16] + status[4][4] arrays). - SYNC + own timer + CM-strobe gating tracks the SRC chip-select latch at X2/X3 (compile-time RAM4002_CHIP_PAIR selects which of 4 chip pairs this instance responds to). - RESET clears storage and drops output port to 0. Not yet implemented (Phase D-2 follow-up): full SRC + WRM/RDM/WR0..3/ RD0..3 round-trip with the 4004. The 4004 chip currently stubs those I/O instructions, so even though the 4002's address-latching works, no data ever flows. Requires modifying 4004.c to drive the bus during X2/X3 of SRC and during M2 of the I/O group. Tests: 2/2 passing (pin contract + RESET behaviour). Total test_intel: 111→113 passing. The 4-chip 4004 ecosystem (4001 + 4002 + 4004 + canvas-deployable variants) now exists. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero
parent
555a4315be
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d5ab6ba6b9
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@ -649,17 +649,22 @@ A small state machine (S_SAMPLE_LOW → S_SAMPLE_MID → S_SAMPLE_HIGH →
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S_DRIVE_HI → S_DRIVE_LO → S_POST) handles the 8-phase walk; reset on
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SYNC rising. Documented in `4001-rom.c`.
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### Deferred — still pending
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- **4002 RAM** — similar 16-pin chip. Needs SRC-instruction tracking
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(the 4004 latches an 8-bit chip-select into the 4002 during X2/X3
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of the SRC cycle, then subsequent WRM/RDM/WMP/RDR ops use that
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latched address). Moderate complexity; same timing model as 4001.
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- **4004 SRC + WRM/RDM/WMP wiring** to actually exchange data with a
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4002. The 4004 chip currently STUBS these as no-ops; needs to drive
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the bus during X2/X3 of SRC and during M2 of the I/O group ops.
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### Phase D — 4002 also delivered (2026-04-30 → 2026-05-01)
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- **4002 RAM** (`test_buses/4002-ram.c`, ~150 LOC) — companion data/IO
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chip. 16-pin contract, 80-nibble main + status storage, 4-pin output
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port, SYNC-driven phase tracking + CM-strobe-gated SRC chip-select
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latching at X2/X3. RESET clears storage and output port. 2/2 unit
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tests pass.
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### Phase D — still pending
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- **4004 SRC + WRM/RDM/WMP wiring** — the 4004 chip currently stubs
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the I/O group instructions; for the 4002 to actually receive
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addresses and exchange data, the 4004's SRC must drive the bus
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during X2/X3 and the I/O group ops must drive/sample during M2.
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Full I/O-group end-to-end is a Phase D-2 follow-up.
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- **Busicom 141-PF integration test** for 4004 — requires both 4001
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and 4002 working end-to-end, plus a baked Busicom firmware ROM
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variant (~1 KB).
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and 4002 working end-to-end (i.e. Phase D-2 complete) plus a baked
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Busicom firmware ROM variant (~1 KB).
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### Tests delta
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- Total test_intel: 98 → **99 passing**, 11 todo, 0 failed.
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@ -0,0 +1,189 @@
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/*
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* Intel 4002 RAM — companion data/IO chip for the 4004/4040.
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*
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* 16-pin DIP, 80 nibbles of static RAM (4 registers × 20 chars: 16
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* main + 4 status), plus 4 dedicated output port lines driven by WMP.
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* Like the 4001 ROM, the 4002 uses the multiplexed nibble bus and
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* tracks the 4004's 8-phase frame via SYNC + an internal timer.
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*
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* Source: Intel MCS-4 User's Manual (Feb 1973), §V "4002 Random
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* Access Memory" + Fig. 5-15 pin diagram.
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*
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* Pin contract (we register 14 named pins; some 4002 variants have
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* additional power rails we collapse):
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* D0..D3 I/O shared multiplexed bus with the 4004
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* O0..O3 out dedicated output port (driven by WMP)
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* SYNC in cycle marker driven by the 4004
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* CL in Φ2 clock — informational
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* RESET in asynchronous reset — clears storage
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* CM in chip-match strobe (one of CM-RAM0..3)
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* VDD, VSS power
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*
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* Address protocol (the SRC instruction):
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* When the 4004 executes SRC Pn, during X2 of that cycle the bus
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* carries the chip-select address (high nibble of the register
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* pair). During X3 it carries the char address (low nibble). The
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* 4002 latches both, but only retains them if the high nibble's
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* bits 3..2 match the chip's hardcoded chip-pair number AND the
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* strobed CM line is the one this chip is wired to.
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*
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* Subsequent I/O ops (WRM/RDM/WR0..3/RD0..3) use the latched address.
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*
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* For the FIRST cut of this chip:
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* - Storage exists (80 nibbles + 4 status lines).
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* - Pin contract registered.
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* - SRC chip-select latching tracked via SYNC + timer + D-bus
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* observation during the X2/X3 phases (works only when the 4004
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* is modified to actually drive the SRC address — currently the
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* 4004 stubs SRC so this chip's storage is never reached
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* end-to-end. Tracked as a Phase D follow-up.)
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* - WMP write drives the 4 output port pins.
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*
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* NOT yet implemented:
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* - WRR/RDR (these are 4001 ROM-port operations, unrelated to RAM).
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* - Status-character (WR0..WR3 / RD0..RD3) handling beyond raw
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* storage.
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* - Cycle-accurate latch timing across CM strobes.
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*/
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#include "velxio-chip.h"
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#ifndef RAM4002_CHIP_PAIR
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#define RAM4002_CHIP_PAIR 0 /* bits 3..2 of chip-select address */
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#endif
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#define MAIN_CHARS_PER_REG 16
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#define STATUS_PER_REG 4
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#define NUM_REGS 4
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typedef enum {
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S_IDLE = 0,
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S_AFTER_SYNC, /* tracking phases since last SYNC */
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} state_t;
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typedef struct {
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vx_pin d[4];
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vx_pin o[4];
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vx_pin sync;
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vx_pin cl;
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vx_pin reset_;
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vx_pin cm;
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vx_pin vdd, vss;
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vx_timer phase_timer;
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/* 4 registers × 16 main chars + 4 status chars each */
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uint8_t main[NUM_REGS][MAIN_CHARS_PER_REG];
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uint8_t status[NUM_REGS][STATUS_PER_REG];
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uint8_t output_port; /* driven on O0..O3 by WMP */
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/* Latched SRC address. Updated when CM strobe + SRC X2/X3 align. */
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uint8_t latched_reg; /* 0..3 */
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uint8_t latched_char; /* 0..15 */
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bool selected; /* this chip's pair matches the latched reg's high bits */
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state_t state;
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int phase_count; /* phases since last SYNC */
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bool driving_d;
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} chip_t;
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static chip_t G;
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/* ─── D-bus helpers ─────────────────────────────────────────────────────── */
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static uint8_t read_d_nibble(void) {
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uint8_t v = 0;
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for (int i = 0; i < 4; i++) if (vx_pin_read(G.d[i])) v |= (1u << i);
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return v;
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}
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static void drive_d_nibble(uint8_t n) {
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for (int i = 0; i < 4; i++) {
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vx_pin_set_mode(G.d[i], VX_OUTPUT);
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vx_pin_write(G.d[i], (n >> i) & 1);
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}
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G.driving_d = true;
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}
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static void release_d(void) {
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if (!G.driving_d) return;
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for (int i = 0; i < 4; i++) vx_pin_set_mode(G.d[i], VX_INPUT);
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G.driving_d = false;
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}
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static void drive_output(uint8_t v) {
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G.output_port = v & 0x0F;
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for (int i = 0; i < 4; i++) vx_pin_write(G.o[i], (v >> i) & 1);
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}
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/* ─── Phase tracking ────────────────────────────────────────────────────── */
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static void on_phase(void* user_data) {
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(void)user_data;
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if (G.state != S_AFTER_SYNC) return;
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G.phase_count++;
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/* A faithful 4002 latches the SRC chip-select bits at X2 (phase 6
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counting from A1=0) when CM is asserted. Without explicit X2
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opcode tracking from the 4004, we approximate: capture the bus
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contents at phase 6 IF CM is high. */
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if (G.phase_count == 6 && vx_pin_read(G.cm)) {
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uint8_t hi = read_d_nibble(); /* chip# (bits 3..2) | reg# (bits 1..0) */
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G.selected = ((hi >> 2) & 3) == RAM4002_CHIP_PAIR;
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if (G.selected) {
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G.latched_reg = hi & 3;
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}
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} else if (G.phase_count == 7 && G.selected && vx_pin_read(G.cm)) {
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G.latched_char = read_d_nibble() & 0xF;
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}
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}
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static void on_sync(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (value) {
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G.state = S_AFTER_SYNC;
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G.phase_count = 0;
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}
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}
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static void on_reset(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (value) {
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memset(G.main, 0, sizeof G.main);
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memset(G.status, 0, sizeof G.status);
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drive_output(0);
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G.selected = false;
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G.latched_reg = 0;
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G.latched_char = 0;
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release_d();
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}
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}
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void chip_setup(void) {
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char name[5];
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for (int i = 0; i < 4; i++) {
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name[0]='D'; name[1]='0'+i; name[2]=0;
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G.d[i] = vx_pin_register(name, VX_INPUT);
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}
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for (int i = 0; i < 4; i++) {
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name[0]='O'; name[1]='0'+i; name[2]=0;
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G.o[i] = vx_pin_register(name, VX_OUTPUT_LOW);
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}
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G.sync = vx_pin_register("SYNC", VX_INPUT);
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G.cl = vx_pin_register("CL", VX_INPUT);
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G.reset_ = vx_pin_register("RESET", VX_INPUT);
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G.cm = vx_pin_register("CM", VX_INPUT);
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G.vdd = vx_pin_register("VDD", VX_INPUT);
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G.vss = vx_pin_register("VSS", VX_INPUT);
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memset(G.main, 0, sizeof G.main);
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memset(G.status, 0, sizeof G.status);
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G.output_port = 0;
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G.state = S_IDLE;
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G.phase_count = 0;
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G.selected = false;
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G.driving_d = false;
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vx_pin_watch(G.sync, VX_EDGE_RISING, on_sync, 0);
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vx_pin_watch(G.reset_, VX_EDGE_RISING, on_reset, 0);
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G.phase_timer = vx_timer_create(on_phase, 0);
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vx_timer_start(G.phase_timer, 1351, true);
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}
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@ -0,0 +1,47 @@
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/**
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* Intel 4002 RAM — basic unit test.
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*
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* The 4002's full I/O cycle requires the 4004 to actually drive the
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* SRC chip-select address during X2/X3 of the SRC instruction (which
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* the current 4004.c stubs as a no-op). This test exercises only the
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* pin contract and the chip's response to RESET — the canvas-level
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* deliverable. Full SRC + WRM/RDM round-trip is tracked as a Phase D
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* follow-up that requires modifying 4004.c.
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists } from '../src/helpers.js';
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const CHIP = '4002-ram';
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const skip = !chipWasmExists(CHIP);
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function pinMap() {
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const m = {
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SYNC: 'SYNC', CL: 'CL', RESET: 'RESET', CM: 'CM',
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VDD: 'VDD', VSS: 'VSS',
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};
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for (let i = 0; i < 4; i++) m[`D${i}`] = `D${i}`;
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for (let i = 0; i < 4; i++) m[`O${i}`] = `O${i}`;
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return m;
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}
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describe(`${CHIP} chip`, () => {
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let board;
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beforeEach(() => { board = new BoardHarness(); });
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afterEach(() => { board.dispose(); });
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it.skipIf(skip)('registers all 14 logical pins', async () => {
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await expect(board.addChip(CHIP, pinMap())).resolves.toBeDefined();
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});
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it.skipIf(skip)('after RESET output port reads zero', async () => {
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await board.addChip(CHIP, pinMap());
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board.setNet('RESET', true);
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board.advanceNanos(50);
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board.setNet('RESET', false);
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board.advanceNanos(50);
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let out = 0;
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for (let i = 0; i < 4; i++) if (board.getNet(`O${i}`)) out |= (1 << i);
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expect(out).toBe(0);
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});
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});
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