test_intel: 8086 + 8259 PIC end-to-end interrupt integration
First test wiring the 8086 CPU to a real 8259 PIC chip on the same board and proving hardware-interrupt routing works end-to-end: IRQ0 input → PIC asserts INT → CPU's INTR pin → CPU runs INTA cycle → PIC drives vector 0x40 on AD bus → CPU does do_int(0x40) → fetches CS:IP from IVT entry at 0x100 → ISR runs → IRET → main resumes from HLT. Two related chip fixes required to make this work: 1. 8086 INTA cycle no longer drives AD itself. Real 8086 INTA bus cycle has the PIC drive the data lines, not the CPU. My earlier code did `bus_read_byte(0, false)` which first drove AD with addr=0, overwriting whatever the PIC had driven. Fix: release_ad → INTA̅ low → sample AD (PIC's INTA watcher fires synchronously and drives) → INTA̅ high. 2. 8086 HLT now interruptible. on_clock previously early-returned on G.halted, so step() never ran and the INTR check never executed. Real 8086 HLT wakes on INTR/NMI. Fix: remove the early return; step()'s own halted check (later in the function) only no-ops if no pending interrupt. Tests: total test_intel 110 → 111 passing (+1, the integration test). 0 failed. 11 todo. test_8086 now 11→12 passing. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero
parent
479b52634e
commit
555a4315be
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@ -983,13 +983,16 @@ static void step(void) {
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return;
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}
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if (G.intr_line && (G.flags & F_IF)) {
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/* Approximate: read the vector byte from the data bus during
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an INTA cycle. The actual external 8259 PIC would jam the
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vector. Here we synthesise INT 0 if no fixture drives the
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bus (reset state); a test fixture can override by driving
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the data bus when our chip asserts INTA̅ low. */
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/* Hardware interrupt acknowledge cycle. Real 8086 in min mode
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runs two INTA̅ pulses; the second has the data bus driven by
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the external 8259 PIC with the vector byte. We collapse to
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one pulse here. Critically, we must NOT drive AD ourselves
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during this cycle — the PIC owns the bus. */
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release_ad();
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vx_pin_write(G.inta, 0);
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uint8_t vec = bus_read_byte(0, false); /* dummy read for cycle */
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/* PIC's INTA̅-falling-edge watcher fires synchronously and
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drives AD0..AD7 with the vector. Sample. */
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uint8_t vec = (uint8_t)(read_ad() & 0xFF);
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vx_pin_write(G.inta, 1);
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do_int(vec);
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G.halted = false;
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@ -1430,13 +1433,15 @@ static void on_intr(void* user_data, vx_pin pin, int value) {
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static void on_clock(void* user_data) {
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(void)user_data;
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if (G.reset_active) return;
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if (G.halted) return;
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if (vx_pin_read(G.ready) == 0) return; /* wait state */
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if (vx_pin_read(G.hold) == 1) { /* bus hold */
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vx_pin_write(G.hlda, 1);
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return;
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}
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vx_pin_write(G.hlda, 0);
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/* Do NOT early-return on halted — step() handles that and also
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serves an interrupt that wakes us up. Real 8086 HLT is
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interruptible. */
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step();
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}
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@ -0,0 +1,154 @@
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/**
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* 8086 + 8259 PIC integration test.
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*
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* Wires both chips on one board, configures the PIC, fires an
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* IRQ, and verifies the 8086 takes the interrupt and runs an ISR
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* that writes a sentinel byte to memory.
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*
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* This is the first end-to-end test of hardware-interrupt routing
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* from an external chip (the PIC) into the CPU's interrupt
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* pipeline — proving the INTA bus cycle works between two real
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* WASM chips.
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*/
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import { describe, it, expect } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists } from '../src/helpers.js';
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const CPU = '8086';
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const PIC = '8259-pic';
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const skip = !chipWasmExists(CPU) || !chipWasmExists(PIC);
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const CLOCK_NS = 200;
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function cpuPinMap() {
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const m = {
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ALE: 'ALE', RD: 'RD', WR: 'WR', MIO: 'MIO', DTR: 'DTR', DEN: 'DEN',
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HOLD: 'HOLD', HLDA: 'HLDA',
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INTR: 'INTR', NMI: 'NMI', INTA: 'INTA',
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RESET: 'RESET', READY: 'READY', TEST: 'TEST', CLK: 'CLK',
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MNMX: 'MNMX', BHE: 'BHE',
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VCC: 'VCC', GND: 'GND',
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};
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for (let i = 0; i < 16; i++) m[`AD${i}`] = `AD${i}`;
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for (let i = 16; i < 20; i++) m[`A${i}`] = `A${i}`;
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return m;
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}
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function picPinMap() {
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// PIC's D bus is the low byte of the 8086's AD bus. PIC's INT pin
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// wires to CPU's INTR; PIC's INTA pin wires to CPU's INTA̅. PIC has
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// its own A0/CS̅/RD̅/WR̅ — we'd normally wire CS̅ to a chip-select
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// decode line, but for this test we just leave it tied to the test
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// fixture (we toggle it manually).
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const m = {
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A0: 'PIC_A0', CS: 'PIC_CS', RD: 'PIC_RD', WR: 'PIC_WR',
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INT: 'INTR', // ← shared net with CPU's INTR
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INTA: 'INTA', // ← shared net with CPU's INTA̅
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CAS0: 'PIC_CAS0', CAS1: 'PIC_CAS1', CAS2: 'PIC_CAS2', SPEN: 'PIC_SPEN',
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VCC: 'VCC', GND: 'GND',
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};
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// PIC's D0..D7 share with CPU's AD0..AD7
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for (let i = 0; i < 8; i++) m[`D${i}`] = `AD${i}`;
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for (let i = 0; i < 8; i++) m[`IRQ${i}`] = `IRQ${i}`;
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return m;
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}
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describe('8086 + 8259 PIC integration', () => {
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it.skipIf(skip)('IRQ0 fires the ISR which writes a sentinel byte', async () => {
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const board = new BoardHarness();
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// PIC must be added BEFORE the CPU so its INTA-falling watcher
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// fires first per advanceNanos and drives D bus with the vector
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// before the CPU samples AD.
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await board.addChip(PIC, picPinMap());
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await board.addChip(CPU, cpuPinMap());
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// RAM covering the full 1 MB. ISR vector at 0x40 → table entry
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// at physical (0x40 << 2) = 0x100..0x103: { offset_lo, offset_hi,
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// segment_lo, segment_hi }. We make the ISR live at CS=0xF000,
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// IP=0x0200, so vector entry is { 0x00, 0x02, 0x00, 0xF0 }.
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const ram = board.installFake8086Bus({});
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// ISR at physical 0xF0200: write 0xAA to [0x9000], then IRET.
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const isr = [
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0xC6, 0x06, 0x00, 0x90, 0xAA, // MOV byte [0x9000], 0xAA
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0xCF, // IRET
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];
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for (let i = 0; i < isr.length; i++) ram.poke(0xF0200 + i, isr[i]);
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// IVT entry for vector 0x40
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ram.poke(0x100, 0x00);
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ram.poke(0x101, 0x02);
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ram.poke(0x102, 0x00);
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ram.poke(0x103, 0xF0);
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// Boot stub: JMP FAR 0xF000:0x0100 at the reset vector.
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ram.poke(0xFFFF0, 0xEA);
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ram.poke(0xFFFF1, 0x00);
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ram.poke(0xFFFF2, 0x01);
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ram.poke(0xFFFF3, 0x00);
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ram.poke(0xFFFF4, 0xF0);
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// Main program at 0xF0100: STI ; HLT (we'll get interrupted out
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// of the HLT). Actually 8086 HLT continues on interrupt — perfect.
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const main = [
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0xFB, // STI
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0xF4, // HLT
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];
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for (let i = 0; i < main.length; i++) ram.poke(0xF0100 + i, main[i]);
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// Quiet inputs.
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board.setNet('MNMX', true);
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board.setNet('READY', true);
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board.setNet('TEST', true);
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board.setNet('NMI', false);
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board.setNet('HOLD', false);
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board.setNet('PIC_CS', true);
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board.setNet('PIC_RD', true);
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board.setNet('PIC_WR', true);
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for (let i = 0; i < 8; i++) board.setNet(`IRQ${i}`, false);
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// Reset CPU
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 8);
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board.setNet('RESET', false);
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// Helper to write to PIC. We need to NOT collide with the CPU's
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// bus, but during this test the CPU is still mid-reset / running
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// the boot JMP. We'll wait until the CPU is in HLT state (after
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// ~2000 cycles) before driving the PIC, to avoid contention.
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function picWrite(a0, value) {
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board.setNet('PIC_A0', a0 !== 0);
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// We use the AD bus for PIC data writes too (since PIC's D maps
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// to AD0..AD7). The CPU is halted so AD is idle.
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for (let i = 0; i < 8; i++) {
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board.setNet(`AD${i}`, ((value >> i) & 1) === 1);
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}
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board.advanceNanos(20);
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board.setNet('PIC_CS', false);
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board.setNet('PIC_WR', false);
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board.advanceNanos(20);
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board.setNet('PIC_WR', true);
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board.advanceNanos(20);
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board.setNet('PIC_CS', true);
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}
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// Run a few cycles to get past the JMP-FAR + STI + HLT.
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for (let i = 0; i < 2000; i++) board.advanceNanos(CLOCK_NS);
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// Configure PIC: ICW1 (single, ICW4-needed) + ICW2 (vector base 0x40)
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// + ICW4 (8086 mode) + OCW1 (mask = 0).
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picWrite(0, 0x13);
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picWrite(1, 0x40);
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picWrite(1, 0x01);
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picWrite(1, 0x00);
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// Fire IRQ0 — should produce INT, INTA cycle drives 0x40 on bus,
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// CPU executes do_int(0x40), runs the ISR, RETs back.
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board.setNet('IRQ0', true);
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for (let i = 0; i < 5000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9000)).toBe(0xAA);
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board.dispose();
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}, 30_000);
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});
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