246 lines
9.1 KiB
C
246 lines
9.1 KiB
C
/*
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* Intel 4002 RAM — companion data/IO chip for the 4004/4040.
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*
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* 16-pin DIP, 80 nibbles of static RAM (4 registers × 20 chars: 16
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* main + 4 status), plus 4 dedicated output port lines driven by WMP.
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* Like the 4001 ROM, the 4002 uses the multiplexed nibble bus and
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* tracks the 4004's 8-phase frame via SYNC + an internal timer.
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*
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* Source: Intel MCS-4 User's Manual (Feb 1973), §V "4002 Random
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* Access Memory" + Fig. 5-15 pin diagram.
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*
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* Pin contract (we register 14 named pins):
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* D0..D3 I/O shared multiplexed bus with the 4004
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* O0..O3 out dedicated output port (driven by WMP)
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* SYNC in cycle marker driven by the 4004
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* CL in Φ2 clock — informational
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* RESET in asynchronous reset — clears storage
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* CM in chip-match strobe (one of CM-RAM0..3)
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* VDD, VSS power
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*
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* Timing model — like the 4001, this chip is registered BEFORE the
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* 4004 so its on_phase fires first per advanceNanos. Within a cycle
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* the relationship is:
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*
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* absolute frame | 4002 phase_count | bus contents when 4002 fires
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* ----------------|------------------|-----------------------------
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* A1 | (post-sync 0) | (4002 fires before sync rise)
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* A2 | 1 | A1's drive (PC[3:0])
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* A3 | 2 | A2's drive (PC[7:4])
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* M1 | 3 | A3's drive WAS PC[11:8]; the
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* | | 4001 (registered before 4002)
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* | | has just driven opcode_hi
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* M2 | 4 | 4001 just drove opcode_lo
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* | | → full opcode known here
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* X1 | 5 | (idle)
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* X2 | 6 | bus is stale; for read ops
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* | | the 4002 drives D HERE so the
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* | | 4004 (firing next) samples it
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* X3 | 7 | bus = 4004's X2 drive — for
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* | | SRC this is chip-select+reg;
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* | | for WRM/WMP/WR0..3 it's ACC
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* A1-of-next | 8 | bus = 4004's X3 drive — for
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* | | SRC this is char-addr nibble
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*
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* On the next SYNC edge, phase_count resets to 0 and the cycle repeats.
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* The 4001 ROM uses an analogous one-frame-behind state machine.
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*/
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#include "velxio-chip.h"
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#ifndef RAM4002_CHIP_PAIR
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#define RAM4002_CHIP_PAIR 0 /* bits 3..2 of chip-select address */
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#endif
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#define MAIN_CHARS_PER_REG 16
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#define STATUS_PER_REG 4
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#define NUM_REGS 4
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typedef struct {
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vx_pin d[4];
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vx_pin o[4];
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vx_pin sync;
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vx_pin cl;
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vx_pin reset_;
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vx_pin cm;
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vx_pin vdd, vss;
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vx_timer phase_timer;
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/* 4 registers × 16 main chars + 4 status chars each */
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uint8_t main[NUM_REGS][MAIN_CHARS_PER_REG];
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uint8_t status[NUM_REGS][STATUS_PER_REG];
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uint8_t output_port; /* driven on O0..O3 by WMP */
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/* Latched SRC address. Updated when CM strobe + SRC X2/X3 align. */
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uint8_t latched_reg; /* 0..3 */
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uint8_t latched_char; /* 0..15 */
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bool selected; /* this chip's pair matches the latched reg's high bits */
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/* Cycle-tracking state. */
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bool after_sync;
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int phase_count;
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uint8_t cur_opcode; /* assembled at phase_count 3+4 */
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bool driving_d;
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} chip_t;
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static chip_t G;
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/* ─── D-bus helpers ─────────────────────────────────────────────────────── */
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static uint8_t read_d_nibble(void) {
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uint8_t v = 0;
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for (int i = 0; i < 4; i++) if (vx_pin_read(G.d[i])) v |= (1u << i);
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return v;
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}
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static void drive_d_nibble(uint8_t n) {
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for (int i = 0; i < 4; i++) {
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vx_pin_set_mode(G.d[i], VX_OUTPUT);
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vx_pin_write(G.d[i], (n >> i) & 1);
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}
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G.driving_d = true;
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}
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static void release_d(void) {
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if (!G.driving_d) return;
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for (int i = 0; i < 4; i++) vx_pin_set_mode(G.d[i], VX_INPUT);
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G.driving_d = false;
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}
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static void drive_output(uint8_t v) {
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G.output_port = v & 0x0F;
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for (int i = 0; i < 4; i++) vx_pin_write(G.o[i], (v >> i) & 1);
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}
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/* ─── Phase tracking ────────────────────────────────────────────────────── */
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static bool is_src_op(uint8_t op) { return (op & 0xF1) == 0x21; }
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static void on_phase(void* user_data) {
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(void)user_data;
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if (!G.after_sync) return;
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G.phase_count++;
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switch (G.phase_count) {
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case 3:
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/* M1 frame — 4001 drove opcode_hi just before us. */
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G.cur_opcode = (read_d_nibble() & 0xF) << 4;
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break;
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case 4:
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/* M2 frame — opcode_lo. Full opcode known. */
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G.cur_opcode |= read_d_nibble() & 0xF;
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break;
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case 6: {
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/* X2 frame — drive D for read ops BEFORE the 4004 samples.
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Only act if a prior SRC selected us. */
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if (!G.selected) break;
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uint8_t op = G.cur_opcode;
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if (op == 0xE9 /* RDM */ || op == 0xE8 /* SBM */ || op == 0xEB /* ADM */) {
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drive_d_nibble(G.main[G.latched_reg & 3][G.latched_char & 0xF]);
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} else if (op >= 0xEC && op <= 0xEF /* RD0..RD3 */) {
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drive_d_nibble(G.status[G.latched_reg & 3][op & 3]);
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}
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break;
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}
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case 7: {
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/* X3 frame — bus has 4004's X2 drive. */
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uint8_t op = G.cur_opcode;
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if (is_src_op(op)) {
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/* High nibble of pair — chip-select-pair bits are 3..2,
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register-within-chip is bits 1..0. CM gating: the CM
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line is wired to the 4004's CMRAM[cmram_select], and
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the 4004 asserted it during X2 (the prior frame).
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It's still high here. */
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if (vx_pin_read(G.cm)) {
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uint8_t hi = read_d_nibble();
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G.selected = ((hi >> 2) & 3) == RAM4002_CHIP_PAIR;
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if (G.selected) G.latched_reg = hi & 3;
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}
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} else if (G.selected && vx_pin_read(G.cm)) {
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/* Write group — 4004 drove ACC at X2; latch from bus. */
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uint8_t v = read_d_nibble();
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if (op == 0xE0 /* WRM */) {
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G.main[G.latched_reg & 3][G.latched_char & 0xF] = v;
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} else if (op == 0xE1 /* WMP */) {
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drive_output(v);
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} else if (op >= 0xE4 && op <= 0xE7 /* WR0..WR3 */) {
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G.status[G.latched_reg & 3][op & 3] = v;
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}
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/* WRR (0xE2) addresses 4001 ROM ports, not us. */
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}
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/* Whatever we drove at X2 (for reads) is no longer needed —
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release so we don't fight 4004's A1 PC drive next cycle. */
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release_d();
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break;
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}
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case 8: {
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/* A1-of-next-cycle frame — bus has 4004's X3 drive. The
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only op that drives X3 distinct from X2 is SRC (low
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nibble = char addr). */
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if (G.selected && is_src_op(G.cur_opcode)) {
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G.latched_char = read_d_nibble() & 0xF;
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}
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break;
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}
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default:
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break;
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}
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}
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static void on_sync(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (value) {
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G.after_sync = true;
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G.phase_count = 0;
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G.cur_opcode = 0;
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}
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}
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static void on_reset(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (value) {
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memset(G.main, 0, sizeof G.main);
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memset(G.status, 0, sizeof G.status);
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drive_output(0);
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G.selected = false;
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G.latched_reg = 0;
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G.latched_char = 0;
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G.after_sync = false;
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G.phase_count = 0;
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G.cur_opcode = 0;
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release_d();
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}
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}
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void chip_setup(void) {
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char name[5];
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for (int i = 0; i < 4; i++) {
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name[0]='D'; name[1]='0'+i; name[2]=0;
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G.d[i] = vx_pin_register(name, VX_INPUT);
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}
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for (int i = 0; i < 4; i++) {
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name[0]='O'; name[1]='0'+i; name[2]=0;
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G.o[i] = vx_pin_register(name, VX_OUTPUT_LOW);
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}
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G.sync = vx_pin_register("SYNC", VX_INPUT);
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G.cl = vx_pin_register("CL", VX_INPUT);
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G.reset_ = vx_pin_register("RESET", VX_INPUT);
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G.cm = vx_pin_register("CM", VX_INPUT);
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G.vdd = vx_pin_register("VDD", VX_INPUT);
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G.vss = vx_pin_register("VSS", VX_INPUT);
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memset(G.main, 0, sizeof G.main);
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memset(G.status, 0, sizeof G.status);
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G.output_port = 0;
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G.after_sync = false;
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G.phase_count = 0;
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G.cur_opcode = 0;
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G.selected = false;
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G.driving_d = false;
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vx_pin_watch(G.sync, VX_EDGE_RISING, on_sync, 0);
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vx_pin_watch(G.reset_, VX_EDGE_RISING, on_reset, 0);
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G.phase_timer = vx_timer_create(on_phase, 0);
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vx_timer_start(G.phase_timer, 1351, true);
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}
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