48 lines
1.5 KiB
JavaScript
48 lines
1.5 KiB
JavaScript
/**
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* Intel 4002 RAM — basic unit test.
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*
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* The 4002's full I/O cycle requires the 4004 to actually drive the
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* SRC chip-select address during X2/X3 of the SRC instruction (which
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* the current 4004.c stubs as a no-op). This test exercises only the
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* pin contract and the chip's response to RESET — the canvas-level
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* deliverable. Full SRC + WRM/RDM round-trip is tracked as a Phase D
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* follow-up that requires modifying 4004.c.
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists } from '../src/helpers.js';
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const CHIP = '4002-ram';
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const skip = !chipWasmExists(CHIP);
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function pinMap() {
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const m = {
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SYNC: 'SYNC', CL: 'CL', RESET: 'RESET', CM: 'CM',
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VDD: 'VDD', VSS: 'VSS',
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};
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for (let i = 0; i < 4; i++) m[`D${i}`] = `D${i}`;
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for (let i = 0; i < 4; i++) m[`O${i}`] = `O${i}`;
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return m;
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}
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describe(`${CHIP} chip`, () => {
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let board;
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beforeEach(() => { board = new BoardHarness(); });
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afterEach(() => { board.dispose(); });
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it.skipIf(skip)('registers all 14 logical pins', async () => {
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await expect(board.addChip(CHIP, pinMap())).resolves.toBeDefined();
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});
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it.skipIf(skip)('after RESET output port reads zero', async () => {
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await board.addChip(CHIP, pinMap());
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board.setNet('RESET', true);
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board.advanceNanos(50);
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board.setNet('RESET', false);
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board.advanceNanos(50);
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let out = 0;
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for (let i = 0; i < 4; i++) if (board.getNet(`O${i}`)) out |= (1 << i);
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expect(out).toBe(0);
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});
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});
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