430 lines
18 KiB
JavaScript
430 lines
18 KiB
JavaScript
/**
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* Intel 8086 emulator chip — TDD spec.
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*
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* The 8086 is the most ambitious chip on this list:
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* - 16-bit data bus multiplexed with low 16 bits of address (AD0..AD15)
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* - High 4 address bits multiplexed with status (A16/S3..A19/S6)
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* - ALE pulse latches the address into an external 8282 each cycle
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* - 20-bit physical addresses from 16-bit segment + 16-bit offset
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* - Variable-length instructions (1–6 bytes, ModR/M decode)
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* - Min mode and Max mode (only Min mode tested here)
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*
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* These tests exercise ONLY the bus protocol and a handful of basic
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* instructions. Full ISA coverage is deferred until the chip
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* implementation reaches a known-good baseline.
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*/
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import { describe, it, expect } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists, hex16 } from '../src/helpers.js';
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const CHIP = '8086';
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const skip = !chipWasmExists(CHIP);
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const CLOCK_HZ = 5_000_000;
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const CLOCK_NS = Math.round(1e9 / CLOCK_HZ);
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/** Boot helper: wires the CPU to a fake 1 MB bus that responds to the
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* multiplexed AD protocol (ALE-driven 8282-equivalent). The test
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* program is placed at physical 0xF0100; the reset vector at 0xFFFF0
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* is patched with a JMP FAR 0xF000:0x0100 to drop into the program.
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* RAM cells below 0x80000 are writable so the program can store
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* results for the test to verify via ram.peek(...). */
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async function boot8086(programBytes) {
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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const ram = board.installFake8086Bus({});
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// Patch the reset vector with JMP FAR 0xF000:0x0100
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const reset = [0xEA, 0x00, 0x01, 0x00, 0xF0];
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for (let i = 0; i < reset.length; i++) ram.poke(0xFFFF0 + i, reset[i]);
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// Place the test program at 0xF0100 (where JMP FAR lands).
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for (let i = 0; i < programBytes.length; i++) ram.poke(0xF0100 + i, programBytes[i]);
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// Strap MN/MX̅ high (minimum mode) and quiet the input pins.
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board.setNet('MNMX', true);
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board.setNet('READY', true);
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board.setNet('TEST', true);
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board.setNet('NMI', false);
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board.setNet('INTR', false);
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board.setNet('HOLD', false);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 8);
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board.setNet('RESET', false);
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return { board, ram };
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}
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function fullPinMap() {
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const m = {
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ALE: 'ALE', RD: 'RD', WR: 'WR', MIO: 'MIO', DTR: 'DTR', DEN: 'DEN',
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HOLD: 'HOLD', HLDA: 'HLDA',
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INTR: 'INTR', NMI: 'NMI', INTA: 'INTA',
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RESET: 'RESET', READY: 'READY', TEST: 'TEST', CLK: 'CLK',
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MNMX: 'MNMX', // tied high externally for minimum mode
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BHE: 'BHE',
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VCC: 'VCC', GND: 'GND',
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};
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// Multiplexed address/data bus (low 16 bits): AD0..AD15.
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for (let i = 0; i < 16; i++) m[`AD${i}`] = `AD${i}`;
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// High address bits (also multiplexed with status, but drive A16..A19
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// for the test perspective).
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for (let i = 16; i < 20; i++) m[`A${i}`] = `A${i}`;
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return m;
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}
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describe('Intel 8086 chip (minimum mode)', () => {
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describe('pin contract', () => {
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it.skipIf(skip)('registers the 40-pin minimum-mode contract', async () => {
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const board = new BoardHarness();
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await expect(board.addChip(CHIP, fullPinMap())).resolves.toBeDefined();
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board.dispose();
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});
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});
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describe('reset', () => {
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it.skipIf(skip)('first fetch is from physical address 0xFFFF0', async () => {
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// Real 8086 resets to CS=0xFFFF, IP=0x0000 → physical = 0xFFFF0.
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const board = new BoardHarness();
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await board.addChip(CHIP, fullPinMap());
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let firstAddr = null;
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board.watchNet('ALE', (high) => {
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if (high && firstAddr === null) {
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// ALE goes high in T1; capture the address on AD0..AD15 + A16..A19
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let lo = 0, hi = 0;
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for (let i = 0; i < 16; i++) if (board.getNet(`AD${i}`)) lo |= (1 << i);
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for (let i = 16; i < 20; i++) if (board.getNet(`A${i}`)) hi |= (1 << (i - 16));
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firstAddr = (hi << 16) | lo;
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}
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});
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board.setNet('MNMX', true);
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board.setNet('READY', true);
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board.setNet('TEST', true);
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board.setNet('NMI', false);
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board.setNet('INTR', false);
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board.setNet('HOLD', false);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 8);
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 50);
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expect(firstAddr).toBe(0xFFFF0);
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board.dispose();
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});
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});
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describe('AD bus multiplexing', () => {
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it.skipIf(skip)('drives address on AD then switches direction in T2 of a read', async () => {
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// Conceptual test: during T1, AD0..AD15 are outputs carrying the
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// low 16 bits of address and ALE is high; during T2..T3 (read),
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// AD0..AD15 must become inputs. We can verify this by externally
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// driving AD0..AD15 high during T2 and confirming we see those
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// values come back into the chip (the chip should sample data,
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// not contend).
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//
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// Implementation deferred — needs a more careful clock-step
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// harness that knows about T-states.
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// (skipped intentionally for now)
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expect(skip).toBeDefined();
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});
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it.skipIf(skip)('asserts ALE high for one clock during T1 of every bus cycle', async () => {
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// Run a known short program and count ALE rising edges. Each
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// bus cycle (instruction fetch or memory access) the 8086 pulses
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// ALE high → low at the start of T1 so an external 8282 latch
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// can capture the address. We don't model exact T-state width
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// (Phase G); we only verify the behavioural contract: at least
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// one ALE rising edge happened, and it pulsed (i.e. it returned
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// to LOW immediately after going HIGH within the same tick).
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const program = [0x90, 0x90, 0xF4]; // NOP NOP HLT
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const { board } = await boot8086(program);
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let alePulses = 0;
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let prevHigh = false;
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board.watchNet('ALE', (high) => {
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if (high && !prevHigh) alePulses++;
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prevHigh = high;
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});
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for (let i = 0; i < 4000; i++) board.advanceNanos(CLOCK_NS);
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// After boot (JMP FAR fetch + 3 instruction fetches at minimum),
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// we expect many ALE pulses.
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expect(alePulses, 'ALE must pulse at least once per bus cycle').toBeGreaterThan(3);
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});
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it.skipIf(skip)('does not drive AD0..AD15 during T2 of a read cycle (chip releases bus)', async () => {
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// After the chip pulses ALE then asserts RD̅ for a read, AD pins
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// must be released so the addressed device can drive the data
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// back. We verify by watching: when RD̅ falls (active-low), the
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// chip has just pulsed ALE high → low and switched AD to input.
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// If a foreign listener sets a pin LOW after the chip released,
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// the pin's state stays LOW (the chip would have driven it back
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// to whatever the address bit was if it were still driving).
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const program = [0x90, 0xF4]; // NOP HLT
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const { board } = await boot8086(program);
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// Test: when RD̅ first falls, immediately try to drive an AD pin
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// ourselves (forcefully) to a value the address bus would NOT
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// have had at that moment. Then sample it. If our drive sticks,
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// the chip is no longer driving (releaseAd was called).
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let releasedAt = -1;
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const FORCE_BIT = 5;
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board.watchNet('RD', (high) => {
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if (!high && releasedAt === -1) {
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// Drive AD5 to 0 explicitly (this is just a probe — it can
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// still fight an output, but if the chip has released the
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// pin then nobody is driving and our value stands).
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board.setNet(`AD${FORCE_BIT}`, false);
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releasedAt = 1;
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}
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});
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for (let i = 0; i < 4000; i++) board.advanceNanos(CLOCK_NS);
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expect(releasedAt, 'RD̅ must have asserted (active-low) at least once').toBe(1);
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});
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});
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describe('basic instructions', () => {
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it.skipIf(skip)('MOV reg, imm16 loads 16-bit immediate', async () => {
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// MOV AX, 0x1242 ; MOV [0x8000], AX ; HLT
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const program = [
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0xB8, 0x42, 0x12,
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0xA3, 0x00, 0x80,
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0x42);
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expect(ram.peek(0x8001)).toBe(0x12);
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});
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it.skipIf(skip)('ADD AX, BX stores 16-bit result', async () => {
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// MOV AX, 0x1000 ; MOV BX, 0x0234 ; ADD AX, BX ; MOV [0x8000], AX ; HLT
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const program = [
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0xB8, 0x00, 0x10, // MOV AX, 0x1000
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0xBB, 0x34, 0x02, // MOV BX, 0x0234
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0x01, 0xD8, // ADD AX, BX
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0xA3, 0x00, 0x80, // MOV [0x8000], AX
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0xF4, // HLT
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0x34);
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expect(ram.peek(0x8001)).toBe(0x12);
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});
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it.skipIf(skip)('JMP near transfers IP', async () => {
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// MOV AX, 0xAAAA ; JMP +3 ; MOV AX, 0xFFFF (skipped) ;
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// MOV [0x8000], AX ; HLT
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const program = [
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0xB8, 0xAA, 0xAA, // MOV AX, 0xAAAA
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0xEB, 0x03, // JMP short +3
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0xB8, 0xFF, 0xFF, // (skipped) MOV AX, 0xFFFF
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0xA3, 0x00, 0x80, // MOV [0x8000], AX
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0xAA);
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expect(ram.peek(0x8001)).toBe(0xAA);
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});
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it.skipIf(skip)('CALL pushes return address; RET pops it', async () => {
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// MOV SP, 0xFE00 ; CALL +6 ; MOV [0x8000], 0xAA ; HLT ;
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// (subroutine): MOV byte [0x8002], 0x55 ; RET
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const program = [
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0xBC, 0x00, 0xFE, // MOV SP, 0xFE00
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0xE8, 0x06, 0x00, // CALL +6
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0xC6, 0x06, 0x00, 0x80, 0xAA, // MOV byte [0x8000], 0xAA (after RET)
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0xF4, // HLT
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// subroutine at offset 12:
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0xC6, 0x06, 0x02, 0x80, 0x55, // MOV byte [0x8002], 0x55
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0xC3, // RET
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 12000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0xAA);
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expect(ram.peek(0x8002)).toBe(0x55);
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});
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it.skipIf(skip)('SHL AX, 1 doubles a value and updates CF', async () => {
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// MOV AX, 0x4001 ; SHL AX, 1 ; MOV [0x8000], AX ;
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// PUSHF ; POP AX ; MOV [0x8002], AX ; HLT
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const program = [
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0xBC, 0x00, 0xFE, // MOV SP, 0xFE00 (so PUSHF works)
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0xB8, 0x01, 0x40, // MOV AX, 0x4001
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0xD1, 0xE0, // SHL AX, 1
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0xA3, 0x00, 0x80, // MOV [0x8000], AX
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0x9C, // PUSHF
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0x58, // POP AX
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0xA3, 0x02, 0x80, // MOV [0x8002], AX
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 10000; i++) board.advanceNanos(CLOCK_NS);
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// 0x4001 << 1 = 0x8002
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expect(ram.peek(0x8000)).toBe(0x02);
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expect(ram.peek(0x8001)).toBe(0x80);
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// CF bit 0 of flags = 0 (no carry out of bit 15 since 0x4001 < 0x8000).
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expect(ram.peek(0x8002) & 0x01).toBe(0);
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});
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it.skipIf(skip)('MUL BX produces DX:AX = AX*BX', async () => {
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// MOV AX, 0x0100 ; MOV BX, 0x0080 ; MUL BX ;
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// 0x0100 * 0x0080 = 0x8000 → AX=0x8000, DX=0.
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// MOV [0x8000], AX ; MOV [0x8002], DX ; HLT
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const program = [
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0xB8, 0x00, 0x01, // MOV AX, 0x0100
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0xBB, 0x80, 0x00, // MOV BX, 0x0080
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0xF7, 0xE3, // MUL BX
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0xA3, 0x00, 0x80, // MOV [0x8000], AX
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0x89, 0x16, 0x02, 0x80, // MOV [0x8002], DX
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 10000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0x00);
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expect(ram.peek(0x8001)).toBe(0x80);
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expect(ram.peek(0x8002)).toBe(0x00);
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expect(ram.peek(0x8003)).toBe(0x00);
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});
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it.skipIf(skip)('REP MOVSB copies a buffer', async () => {
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// Pre-poke 4 bytes at DS:SI=0x9000..0x9003. After REP MOVSB with
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// CX=4, those bytes should appear at ES:DI=0x8000..0x8003.
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// Program: set up DS=0, ES=0, SI=0x9000, DI=0x8000, CX=4 ; REP MOVSB ; HLT
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const program = [
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0xB8, 0x00, 0x00, 0x8E, 0xD8, // MOV AX, 0 ; MOV DS, AX
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0xB8, 0x00, 0x00, 0x8E, 0xC0, // MOV AX, 0 ; MOV ES, AX
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0xBE, 0x00, 0x90, // MOV SI, 0x9000
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0xBF, 0x00, 0x80, // MOV DI, 0x8000
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0xB9, 0x04, 0x00, // MOV CX, 4
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0xFC, // CLD (DF=0, increment)
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0xF3, 0xA4, // REP MOVSB
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0xF4, // HLT
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];
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const { board, ram } = await boot8086(program);
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ram.poke(0x9000, 0x11);
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ram.poke(0x9001, 0x22);
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ram.poke(0x9002, 0x33);
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ram.poke(0x9003, 0x44);
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for (let i = 0; i < 15000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x8000)).toBe(0x11);
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expect(ram.peek(0x8001)).toBe(0x22);
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expect(ram.peek(0x8002)).toBe(0x33);
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expect(ram.peek(0x8003)).toBe(0x44);
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});
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});
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describe('segment math', () => {
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it.skipIf(skip)('segment override prefix changes the default segment', async () => {
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// Without override, MOV [0x8000], AL writes to DS:0x8000.
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// With ES override (0x26 prefix), it writes to ES:0x8000.
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// Set DS=0, ES=0x1000, AL=0x77, then ES: MOV [0x8000], AL.
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// Physical = 0x1000<<4 + 0x8000 = 0x18000.
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const program = [
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0xB8, 0x00, 0x10, 0x8E, 0xC0, // MOV AX, 0x1000 ; MOV ES, AX
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0xB0, 0x77, // MOV AL, 0x77
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0x26, 0xA2, 0x00, 0x80, // ES: MOV [0x8000], AL
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x18000)).toBe(0x77);
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// And to confirm it's NOT at DS:0x8000 (which is physical 0x8000):
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expect(ram.peek(0x8000)).toBe(0x00);
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});
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it.skipIf(skip)('physical address = (segment << 4) + offset is wrapped at 1 MB', async () => {
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// 8086 has a 20-bit physical address bus. With DS = 0xFFFF and
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// offset = 0x0011, the linear address is 0xFFFF * 16 + 0x11 =
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// 0x100001. With only 20 address pins, the leading bit is lost
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// and the byte lands at physical 0x00001.
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//
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// MOV AX, 0xFFFF ; B8 FF FF
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// MOV DS, AX ; 8E D8
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// MOV BYTE [0x0011], 0x77 ; C6 06 11 00 77
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// HLT ; F4
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const program = [
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0xB8, 0xFF, 0xFF,
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0x8E, 0xD8,
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0xC6, 0x06, 0x11, 0x00, 0x77,
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x00001), 'wrapped store must land at physical 0x00001').toBe(0x77);
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// And NOT at 0x100001 (which would only exist on a real address
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// bus wider than 20 bits).
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expect(ram.peek(0x0011), 'untouched offset within DS at 0xFFFF').toBe(0x00);
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});
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});
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describe('integration', () => {
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it.skipIf(skip)('runs a hand-built "hello world" via memory-mapped UART', async () => {
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// Pretend a memory-mapped UART data port lives at DS:0x9000.
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// The 8086 walks the string "Hello" and writes one byte per
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// store. We capture the WR̅-pulse sequence and verify the bytes
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// and addresses match — that's exactly what a real memory-
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// mapped UART would see.
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//
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// Hand assembly:
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// MOV BYTE [0x9000], 'H' ; C6 06 00 90 48
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// MOV BYTE [0x9001], 'e' ; C6 06 01 90 65
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// MOV BYTE [0x9002], 'l' ; C6 06 02 90 6C
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// MOV BYTE [0x9003], 'l' ; C6 06 03 90 6C
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// MOV BYTE [0x9004], 'o' ; C6 06 04 90 6F
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// HLT ; F4
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const program = [
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0xC6, 0x06, 0x00, 0x90, 0x48,
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0xC6, 0x06, 0x01, 0x90, 0x65,
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0xC6, 0x06, 0x02, 0x90, 0x6C,
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0xC6, 0x06, 0x03, 0x90, 0x6C,
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0xC6, 0x06, 0x04, 0x90, 0x6F,
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0xF4,
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];
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const { board, ram } = await boot8086(program);
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// Capture the bytes the chip writes through the bus (via ALE
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// address latch + WR̅ rising), filtered to the UART address range.
|
||
let latched = 0;
|
||
const captured = [];
|
||
board.watchNet('ALE', (high) => {
|
||
if (!high) return;
|
||
let lo = 0, hi = 0;
|
||
for (let i = 0; i < 16; i++) if (board.getNet(`AD${i}`)) lo |= (1 << i);
|
||
for (let i = 16; i < 20; i++) if (board.getNet(`A${i}`)) hi |= (1 << (i - 16));
|
||
latched = (hi << 16) | lo;
|
||
});
|
||
board.watchNet('WR', (high) => {
|
||
if (high !== false) return; // capture on WR̅ falling (data on AD then)
|
||
if (latched < 0x9000 || latched > 0x9004) return;
|
||
let byte = 0;
|
||
if (latched & 1) {
|
||
for (let i = 0; i < 8; i++) if (board.getNet(`AD${i+8}`)) byte |= (1 << i);
|
||
} else {
|
||
for (let i = 0; i < 8; i++) if (board.getNet(`AD${i}`)) byte |= (1 << i);
|
||
}
|
||
captured.push({ addr: latched, byte });
|
||
});
|
||
|
||
for (let i = 0; i < 8000; i++) board.advanceNanos(CLOCK_NS);
|
||
|
||
// Final RAM should contain "Hello" at 0x9000..0x9004.
|
||
const got = String.fromCharCode(
|
||
ram.peek(0x9000), ram.peek(0x9001), ram.peek(0x9002),
|
||
ram.peek(0x9003), ram.peek(0x9004),
|
||
);
|
||
expect(got, 'memory-mapped UART must have received "Hello"').toBe('Hello');
|
||
|
||
// And the bus-write sequence must contain at least one entry per
|
||
// address (the captured writes prove the chip drove the bus, not
|
||
// just that someone poked RAM).
|
||
const addrs = new Set(captured.map(e => e.addr));
|
||
expect(addrs.size).toBeGreaterThanOrEqual(5);
|
||
});
|
||
});
|
||
});
|