254 lines
8.7 KiB
C
254 lines
8.7 KiB
C
/*
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* Intel 8251 USART — basic asynchronous-mode UART.
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*
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* The 8251 is a 28-pin DIP that gives a CPU programmable serial I/O.
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* The full datasheet covers two operating modes (asynchronous and
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* synchronous), parity, multi-byte init sequence (mode word + sync
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* chars + command word), and a swarm of modem-control pins. This
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* implementation handles the common subset:
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* - Async mode, 8-data-bits, 1 stop bit, no parity (the 90% case)
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* - Mode word loaded once after RESET
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* - Command word: TxEnable / RxEnable / DTR / RTS / Reset
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*
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* Bit-banging of TxD / RxD is delegated to the velxio runtime via
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* `vx_uart_attach` — same mechanism used by the existing uart-rot13
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* example chip. Baud rate is derived from the divisor in the mode word
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* (we hardcode 9600 if not initialised; runtime scales internally).
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*
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* Pin contract:
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* D0..D7 bidirectional
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* RD̅, WR̅ active-low strobes
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* CS̅ active-low chip enable
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* C/D̅ 0 = data register, 1 = control register (mode/command/status)
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* RESET active-high (clears state, returns to "expecting mode word")
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* CLK input clock (informational; we use the runtime's bit timing)
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* TxD, RxD serial lines
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* TxRDY, RxRDY, TxEMPTY status outputs
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* DSR̅, DTR̅, CTS̅, RTS̅ modem-control pins (passed-through; not
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* interpreted by this minimal implementation)
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* VCC, GND
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*
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* The status register at C/D̅=1, RD̅:
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* bit 0 TxRDY (1 = ready to accept next byte)
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* bit 1 RxRDY (1 = received byte available)
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* bit 2 TxEMPTY (1 = transmitter idle)
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* bits 3..7 framing/parity error / SYNDET / DSR̅ — we report 0
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*/
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#include "velxio-chip.h"
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#include <stdint.h>
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#include <stdbool.h>
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typedef enum {
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INIT_EXPECT_MODE = 0,
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INIT_EXPECT_COMMAND,
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INIT_RUNNING,
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} init_state_t;
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typedef struct {
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vx_pin d[8];
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vx_pin rd, wr, cs, cd;
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vx_pin reset_;
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vx_pin clk;
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vx_pin txd, rxd;
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vx_pin tx_rdy, rx_rdy, tx_empty;
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vx_pin dsr, dtr, cts, rts;
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vx_pin vcc, gnd;
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vx_uart uart;
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/* Internal state */
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init_state_t init_state;
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uint8_t mode_word;
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uint8_t command_word;
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uint8_t rx_byte;
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bool rx_ready;
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bool tx_enabled;
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bool rx_enabled;
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bool tx_busy;
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bool driving_d;
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int wr_last;
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} chip_t;
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static chip_t G;
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/* ─── D bus ─────────────────────────────────────────────────────────────── */
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static uint8_t read_d(void) {
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uint8_t v = 0;
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for (int i = 0; i < 8; i++) if (vx_pin_read(G.d[i])) v |= (1u << i);
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return v;
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}
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static void drive_d(uint8_t v) {
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for (int i = 0; i < 8; i++) {
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vx_pin_set_mode(G.d[i], VX_OUTPUT);
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vx_pin_write(G.d[i], (v >> i) & 1);
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}
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G.driving_d = true;
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}
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static void release_d(void) {
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if (!G.driving_d) return;
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for (int i = 0; i < 8; i++) vx_pin_set_mode(G.d[i], VX_INPUT);
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G.driving_d = false;
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}
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static uint8_t status_byte(void) {
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uint8_t v = 0;
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if (!G.tx_busy && G.tx_enabled) v |= 0x01; /* TxRDY */
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if (G.rx_ready) v |= 0x02; /* RxRDY */
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if (!G.tx_busy) v |= 0x04; /* TxEMPTY */
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return v;
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}
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static void update_status_pins(void) {
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vx_pin_write(G.tx_rdy, (G.tx_enabled && !G.tx_busy) ? 1 : 0);
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vx_pin_write(G.rx_rdy, G.rx_ready ? 1 : 0);
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vx_pin_write(G.tx_empty, !G.tx_busy ? 1 : 0);
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}
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/* ─── UART callbacks ────────────────────────────────────────────────────── */
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static void on_rx_byte(void* user_data, uint8_t byte) {
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(void)user_data;
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if (!G.rx_enabled) return;
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G.rx_byte = byte;
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G.rx_ready = true;
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update_status_pins();
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}
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static void on_tx_done(void* user_data) {
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(void)user_data;
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G.tx_busy = false;
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update_status_pins();
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}
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/* ─── RD / WR strobes ───────────────────────────────────────────────────── */
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static void on_rd(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (vx_pin_read(G.cs) != 0) { release_d(); return; }
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if (value != 0) { release_d(); return; }
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if (vx_pin_read(G.cd)) {
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/* Status read */
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drive_d(status_byte());
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} else {
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/* Data read — return the latched RX byte; clear RxRDY. */
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drive_d(G.rx_byte);
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G.rx_ready = false;
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update_status_pins();
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}
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}
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static void on_wr(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (vx_pin_read(G.cs) != 0) { G.wr_last = value; return; }
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if (G.wr_last == 0 && value == 1) {
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uint8_t v = read_d();
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if (vx_pin_read(G.cd)) {
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/* Control write: mode or command depending on state. */
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switch (G.init_state) {
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case INIT_EXPECT_MODE:
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G.mode_word = v;
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/* We only support async mode (bits 0-1 = baud-rate
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factor != 0) in this implementation. We don't
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parse parity / sync. */
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G.init_state = INIT_EXPECT_COMMAND;
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break;
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case INIT_EXPECT_COMMAND:
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case INIT_RUNNING:
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G.command_word = v;
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G.tx_enabled = (v & 0x01) != 0;
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G.rx_enabled = (v & 0x04) != 0;
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/* Bit 6 = internal reset: returns to expecting mode word. */
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if (v & 0x40) {
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G.init_state = INIT_EXPECT_MODE;
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G.tx_enabled = false;
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G.rx_enabled = false;
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} else if (G.init_state == INIT_EXPECT_COMMAND) {
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G.init_state = INIT_RUNNING;
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}
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/* DTR / RTS pass-through to pins (active low). */
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vx_pin_write(G.dtr, (v & 0x02) ? 0 : 1);
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vx_pin_write(G.rts, (v & 0x20) ? 0 : 1);
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update_status_pins();
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break;
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}
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} else {
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/* Data write: queue a byte for transmission. */
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if (G.tx_enabled) {
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G.tx_busy = true;
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vx_uart_write(G.uart, &v, 1);
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update_status_pins();
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}
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}
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}
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G.wr_last = value;
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}
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static void on_reset(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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if (value) {
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G.init_state = INIT_EXPECT_MODE;
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G.tx_enabled = false;
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G.rx_enabled = false;
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G.tx_busy = false;
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G.rx_ready = false;
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G.mode_word = 0;
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G.command_word = 0;
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update_status_pins();
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release_d();
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}
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}
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void chip_setup(void) {
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char name[8];
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for (int i = 0; i < 8; i++) {
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name[0]='D'; name[1]='0'+i; name[2]=0;
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G.d[i] = vx_pin_register(name, VX_INPUT);
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}
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G.rd = vx_pin_register("RD", VX_INPUT);
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G.wr = vx_pin_register("WR", VX_INPUT);
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G.cs = vx_pin_register("CS", VX_INPUT);
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G.cd = vx_pin_register("CD", VX_INPUT);
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G.reset_ = vx_pin_register("RESET", VX_INPUT);
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G.clk = vx_pin_register("CLK", VX_INPUT);
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G.txd = vx_pin_register("TXD", VX_OUTPUT_HIGH);
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G.rxd = vx_pin_register("RXD", VX_INPUT);
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G.tx_rdy = vx_pin_register("TXRDY", VX_OUTPUT_LOW);
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G.rx_rdy = vx_pin_register("RXRDY", VX_OUTPUT_LOW);
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G.tx_empty = vx_pin_register("TXEMPTY", VX_OUTPUT_HIGH);
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G.dsr = vx_pin_register("DSR", VX_INPUT);
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G.dtr = vx_pin_register("DTR", VX_OUTPUT_HIGH);
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G.cts = vx_pin_register("CTS", VX_INPUT);
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G.rts = vx_pin_register("RTS", VX_OUTPUT_HIGH);
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G.vcc = vx_pin_register("VCC", VX_INPUT);
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G.gnd = vx_pin_register("GND", VX_INPUT);
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G.init_state = INIT_EXPECT_MODE;
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G.tx_enabled = false;
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G.rx_enabled = false;
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G.tx_busy = false;
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G.rx_ready = false;
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G.driving_d = false;
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G.wr_last = 1;
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/* Attach to the UART-bus abstraction. The runtime handles bit-level
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timing; we just queue bytes via vx_uart_write and receive via
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on_rx_byte. */
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vx_uart_config cfg = {
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.rx = G.rxd,
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.tx = G.txd,
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.baud_rate = 9600,
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.on_rx_byte = on_rx_byte,
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.on_tx_done = on_tx_done,
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.user_data = 0,
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.reserved = {0,0,0,0,0,0,0,0},
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};
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G.uart = vx_uart_attach(&cfg);
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update_status_pins();
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vx_pin_watch(G.rd, VX_EDGE_BOTH, on_rd, 0);
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vx_pin_watch(G.wr, VX_EDGE_BOTH, on_wr, 0);
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vx_pin_watch(G.reset_, VX_EDGE_RISING, on_reset, 0);
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}
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