velxio/scripts
David Montero 4e20d03f4c feat(sim): P1 over-voltage for boards + electrolytic capacitors
Extends the over-voltage rule to the two cases the previous slice deferred:

- Boards (ESP32 / Pico / Arduino / ...): a board's supply pins all collapse to
  the self-driven vcc_rail net, so an external source on them makes the .op
  singular rather than readable. Added a graph-based check (runs before the
  solve): if a power source is wired to a board supply pin and its nominal
  voltage exceeds that pin's rating, warn. Threaded boardKind into
  BoardForSpice so the verifier can look up the board rating.
- Electrolytic capacitors: new `voltage` rating property (select, default 25V,
  on capacitor-electrolytic + cap-elec-* presets, via component-overrides +
  regenerated metadata). The verifier reads the DC voltage across the +/- pins
  and warns on over-voltage (vent/burst) and on reverse polarity (a polarized
  cap wired backwards). Defaults to 25V when the property is unset.

Tests: 9V battery -> ESP32 VIN warns, 1.5V doesn't; 24V across a 16V cap warns,
5V across a 25V cap doesn't; reverse-biased cap warns. All real-ngspice.
2026-06-18 01:19:13 +02:00
..
asm8080.py feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
component-overrides.json feat(sim): P1 over-voltage for boards + electrolytic capacitors 2026-06-18 01:19:13 +02:00
counter-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
counter-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
generate-component-metadata.ts feat(components): make KY-040 rotary encoder discoverable + add example (#104) 2026-05-31 14:30:59 -03:00
generate-component-svgs.cjs fix(scripts): generate-component-svgs no longer skips bmp280 / fails on ssd1306 2026-05-09 00:05:28 -03:00
generate-example-screenshots.md
generate-favicons.mjs
generate-og-image.mjs
generate-sitemap.ts
killbits-rom.s feat(chips): programmable retro CPU chips with external ROM 2026-05-18 23:38:18 -03:00
larson-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
make-z80-cpu.py fix(z80-cpu): map RAM over the whole 0x8000-0xFFFF so vanilla SDCC C runs 2026-06-03 13:31:26 +02:00
repl-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
repl-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
test-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
visual-led-test.mjs test(visual-led): add RGB + 7-segment leafCheck assertions 2026-05-18 22:39:01 -03:00