velxio/scripts
David Montero Crespo 6307aed007 feat: breadboard (full 830-point) + mini breadboard (170-point) parts
Two velxio-native passive parts, rendered as web components with
programmatic SVG + precomputed pinInfo (velxio-breadboard 830 holes,
velxio-breadboard-mini 170). Pin names follow the Wokwi convention
(holes `18t.d` / `17b.i`, rails `tp/tn/bp/bn.N`) and the metadata ids
are `breadboard` / `breadboard-mini`, so wokwi diagram.json zips
import/export with no aliasing.

Internal connectivity (5-hole column strips, full-length power rails)
is centralized in utils/breadboardNets.ts and wired into every net
consumer:
- NetlistBuilder: unionBreadboardGroups joins wired holes per group at
  the union-find level in buildNetlist, buildWireNetMap and
  buildBoardPinNetMap — SPICE, the circuit verifier and the voltage
  overlay all see one net per strip/rail with no extra cards.
- DynamicComponent.traceDetailed: the digital trace hops through every
  other wired hole of the entered group, so parts wired through a
  breadboard still resolve their board pin (2-terminal
  PASSIVE_PIN_PAIRS could not express N-hole groups).

Verified end-to-end in the app: Uno pin 8 -> full-board column ->
resistor -> mini-board column -> LED -> ground rail -> GND lights the
LED, and the HUD shows the 3 collapsed SPICE nets. 8 new unit tests
(breadboard-nets.test.ts); netlist-builder + circuit-verifier suites
stay green.
2026-07-15 21:50:36 +02:00
..
asm8080.py feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
component-overrides.json feat: breadboard (full 830-point) + mini breadboard (170-point) parts 2026-07-15 21:50:36 +02:00
counter-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
counter-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
generate-component-metadata.ts feat(components): make KY-040 rotary encoder discoverable + add example (#104) 2026-05-31 14:30:59 -03:00
generate-component-svgs.cjs fix(scripts): generate-component-svgs no longer skips bmp280 / fails on ssd1306 2026-05-09 00:05:28 -03:00
generate-example-screenshots.md
generate-favicons.mjs
generate-og-image.mjs
generate-sitemap.ts
killbits-rom.s feat(chips): programmable retro CPU chips with external ROM 2026-05-18 23:38:18 -03:00
larson-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
make-z80-cpu.py fix(z80-cpu): map RAM over the whole 0x8000-0xFFFF so vanilla SDCC C runs 2026-06-03 13:31:26 +02:00
repl-rom.s feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
repl-rom.txt feat(chips): port retro Intel/Zilog CPUs as Velxio custom chips + 2 demos 2026-05-18 02:27:53 -03:00
test-z80.s feat(chips): programmable Z80 chip + Larson scanner example 2026-05-19 00:21:08 -03:00
visual-led-test.mjs test(visual-led): add RGB + 7-segment leafCheck assertions 2026-05-18 22:39:01 -03:00