Commit Graph

4 Commits

Author SHA1 Message Date
davidmonterocrespo24 ebace63ae5 fix(test): pi3 bme280 attach test sys.path + block-read race
Two small fixes after running the test inside the prod container for
the first time:

- The prod image lays out the backend at /app/app/, not /app/backend/app/
  (the Dockerfile.standalone COPYs only the inner package). Use /app
  as the sys.path root so `from app.pro.services import ...` resolves.
- The CHIP=0x60 and BLOCK= prints race against the socket drain. The
  test was treating "saw CHIP= but BLOCK= not in buffer yet" as a
  hard failure and exiting before the second I2C read finished.
  Gate the success path on both markers present and keep polling
  otherwise.

Verified end-to-end in the prod container:

    [proto] >>> ['I2C', '1', '76', 'RR', 'd0', '1']
    [proto] <<< I2C_DATA 1 76 60
    [proto] >>> ['I2C', '1', '76', 'RR', 'f7', '8']
    [proto] <<< I2C_DATA 1 76 530280155e607b50
    [test] OK — guest read chip ID = 0x60
    [test] OK — block read BLOCK=530280155e607b50

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-18 20:39:12 +02:00
davidmonterocrespo24 2072011fa4 feat(pi): pluggable slave handler + canvas wire detection for I2C/SPI/UART
Adds the public extension points the velxio-prod overlay uses to bind
real canvas-side I2C/SPI/UART models (BME280, future MCP23017, etc.)
to a running Pi guest's protocol shims:

- qemu_manager: set_pi_slave_handler(fn) / get_pi_slave_handler() for
  pi_attach_slave + pi_detach_slave WebSocket messages. OSS image
  leaves the hook unset so the messages are silently dropped.
- simulation route: parses the two new WS message types and forwards
  them to the registered handler when present.
- RaspberryPi3Bridge: attachSlave(spec) / detachSlave(spec) frontend
  side of the protocol.
- piSlaveScanner: at simulation start walks components + wires,
  identifies I2C/SPI/UART peers wired to Pi protocol pins (40-pin
  header physical-pin numbering), and emits one attach per
  bus/address pair (deduped across SDA+SCL wires).
- RaspberryPiWorkspace: invokes the scanner once the bridge is open,
  with retries to ride out the WS-still-connecting race.
- integration test: pi3_bme280_attach.py boots the Pi, pre-attaches a
  BME280 via the slave handler, runs a host-side proto loop, runs
  guest python smbus2.read_byte_data(0x76, 0xD0) and asserts the
  console reads back CHIP=0x60.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-18 16:26:37 +02:00
davidmonterocrespo24 ca2b76f1f8 test(pi3): fix Phase 2 E2E test + bump rootfs to shims-final
The Phase 2 E2E test was sending the Python GPIO command via
'python3 -c "..."' but bash quote-nesting silently corrupted the
script — the python process started, printed nothing, exited 0, and
the test asserted 'GPIO_SETUP 17 out' was missing in proto bytes
(it never got sent because the python script never ran).

Switch the test to base64-encode the script + pipe through base64 -d
into a file, then execute. Verified end-to-end now:

  [test] proto received 36 bytes:
      GPIO_SETUP 17 out pud_off
      GPIO 17 1
  [test] ✓ shim → proto pipeline works

Also bump the rootfs manifest entry to the final Phase 2 build
(d6d4a274 raw / debd1c33 zst, version 2026.05+phase2-shims-final).

Earlier auto-discovery in _transport.py was hanging at import time
on some glob/sysfs interaction. Now hardcoded /dev/vport1p1 which
is the empirical path under -M virt + virtio-blk-pci on slot 0.
2026-05-18 15:00:21 +02:00
davidmonterocrespo24 eac845005c feat(pi3 phase 2): bump rootfs to autodiscovery shims + E2E test
The Phase 2 shim originally hardcoded CHARDEV_PATH = /dev/vport0p2.
With QEMU 10 -M virt + virtio-blk-pci consuming slot 0, the proto
port actually lands at /dev/vport1p1 (or further). _transport.py
now walks /sys/class/virtio-ports/*/name looking for the literal
qemu name 'velxio-protocol' set by qemu_manager.

test/pi3_protocols/test_pi3_protocols.py end-to-end runner:
  1. Boot QEMU virt + pipe chardev (same args as production)
  2. Connect cons TCP socket + open both ends of the FIFO pair
  3. Wait for agetty autologin
  4. Run 'import RPi.GPIO; setup(17, OUT); output(17, 1)' in guest
  5. Read FIFO.out, assert 'GPIO_SETUP 17 out' + 'GPIO 17 1' appeared.

Catches: shim path resolution wrong, pipe chardev regression,
mux protocol drift, site-packages overlay broken.
2026-05-18 07:05:12 +02:00