Apply the same xact_t pattern from the 4004 (phase D-2) to the 4040,
so SRC and the I/O group (WRM/WMP/WRR/WPM/WR0..3/SBM/RDM/RDR/ADM/
RD0..3) drive or sample the multiplexed nibble bus during X2/X3 with
CM-RAM (or CM-ROM for ROM-port ops) strobed.
The 4040's two CM-ROM lines (selected by rom_bank) and its STP/INT
control flow are unchanged — the bus action is staged at M2 and
acted on at X2/X3, fitting cleanly inside the existing PHASE_X3
control-flow block.
Two new integration tests under "4040 + 4002 RAM integration" mirror
the 4004's: SRC + WMP drives the output port, and SRC + WRM/RDM
round-trips a nibble through 4002 storage.
Total test_intel: 117 passing, 11 todo, 0 failed (was 115).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
The 4040 is a binary-compatible superset of the 4004. This commit:
- Adds the full 4004 ISA into 4040.c (LD/XCH/INC/ADD/SUB/JCN/JUN/
JMS/BBL/FIM/FIN/JIN/SRC/ISZ/LDM/I-O/ACC group/DAA/KBP/etc.) so the
4040 actually executes user code, not just NOPs.
- Adds the 14 4040-only opcodes per MCS-40 p. 1-22 at OPR=0000
OPA=0x01..0x0E:
HLT, BBS, LCR, OR4, OR5, AN6, AN7, DB0, DB1, SB0, SB1, EIN, DIN,
RPM (4289 stub).
- Implements bank-aware register access — physical reg[0..7] is
bank 0's R0..R7, reg[8..15] is shared R8..R15, reg[16..23] is
bank 1's R0..R7. SB0/SB1 toggle the active R0..R7 mapping.
- 7-deep PC stack (vs 4004's 3-deep) per MCS-40 p. 1-12.
- Interrupt vectoring already in place from prior commit; BBS now
pops PC and clears INTA.
3 it.todo tests promoted to passing:
- INT high after EIN vectors PC to 0x003 and asserts INTA.
- BBS pops PC and clears INTA.
- SB1 + FIM writes to bank-1 R0..R7 (verified by ISZ wrap behaviour:
bank-0 R0=F → ISZ wraps to 0 → no branch, distinguishing from a
buggy SB1 that would have aliased the write to bank 0).
Adds Bus4040 helper (parallel to Bus4004) for feeding opcodes via
the multiplexed nibble bus. Total test_intel: 55 passing (was 52),
0 failed, 22 todo.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
The two earliest commercial Intel CPUs as velxio custom chips:
- 4004.c (~150 LOC): 16-pin DIP, 8-phase frame (A1..X3), SYNC at A1
with PC nibble walk on D0..D3 (low-first per MCS-4 Fig. 2), CMROM
strobe during M1. ISA decoded as NOP for now — full 46-instruction
set deferred to ISA phase.
- 4040.c (~250 LOC): 24-pin DIP per MCS-40 pp. 1-5/1-6 (STP/STPA/INT/
INTA/CY/dual CMROM/dual standby Vdd). 4004-compatible bus + STP
latched at M2 → STPA asserts at X3 + INT forced JMS to PC=0x003.
14 new opcodes decoded as NOP for now.
Test refinements (analogous to bootCpu fix from 8080 work):
- bootChip no longer advances time post-RESET so first observed cycle
starts at A1 of cycle 0 with PC=0.
- SYNC sampler latches on first edge (was over-collecting on
subsequent SYNC pulses).
- 4040 test renamed STOP→STP, STOPACK→STPA per MCS-40 datasheet pin
names; added INTA, CY, VDD1, VDD2 pins; SYNC-stops assertion
removed (manual: STOP mode keeps clock and SYNC running).
Brings test_intel suite from 37 to 43 passing tests; 0 failures;
remaining 3 active are 8086 (deferred), 29 todo are intentional
deferred integration tests.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
David Montero