feat(cyw43): host-wake IRQ + F2 frame byte-order + SET/GET fix
Unblocks the full wifi_on IOCTL sequence in the boot harness (clm_load through the 23-IOCTL bring-up, no crash): - Drive WL_HOST_WAKE (GPIO24, active-high): the driver gates poll_device on this pin until its first packet (had_successful_packet), so without it the first IOCTL response is never read. Emulator now exposes onHostWake(level) and toggles it with the inbound-frame queue. - Encode F2/SDPCM frame reads per 32-bit word (encodeFrameWords), same as register reads: the DMA-in sets channel bswap=true, so an un-encoded frame landed byte-reversed -> header_length read back as garbage and the driver dereferenced ioctl_header at an unaligned address (crash). Guarded to boot mode pass-through (no F2 traffic there; keeps unit tests). - Fix SET/GET detection: SDPCM_SET is bit 1 (0x2), not 0x1; echo the kind bit in IOCTL responses. - Add IOCTL/SDPCM debug counters + sequence log for the harness. Harness (investigation, CYW43_HARNESS=1 only): non-dropping TX FIFO so large F2 writes are not truncated, crank PIO steps/tick so the firmware drains in wall-clock, GPIO24 host-wake wiring, CPU-fault + PC-histogram + PIO-state instrumentation. Remaining: stall after mcast_list (#22) inside cyw43_cb_tcpip_init.
This commit is contained in:
David Montero
parent
b172cadbc5
commit
c4cbb17591
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@ -86,7 +86,21 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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}>((resolve) => {
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const sim = new Simulator();
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sim.rp2040.loadBootrom(bootromB1);
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sim.rp2040.logger = new ConsoleLogger(LogLevel.Error);
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// Custom non-throwing logger: capture CPU faults (e.g. unaligned reads)
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// with the PC so we can locate corruption WITHOUT aborting the run.
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void LogLevel; void ConsoleLogger;
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let faultCount = 0;
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const faultLog: string[] = [];
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sim.rp2040.logger = {
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debug() {}, info() {}, warn() {},
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error: (_comp: string, msg: string) => {
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faultCount++;
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if (faultLog.length < 25) {
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const pc = ((sim.rp2040 as any).core?.PC ?? 0) >>> 0;
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faultLog.push(`PC=0x${pc.toString(16)} ${msg}`);
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}
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},
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} as any;
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const fwBlocks = loadUF2(new Uint8Array(readFileSync(FW_PATH)), sim.rp2040.flash);
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let usbConnected = false;
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@ -104,6 +118,9 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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const rawWords: number[] = [];
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const trace: string[] = [];
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const f2Log: string[] = []; // F2/IOCTL transfers, NOT subject to the ring
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const postF2: string[] = []; // verbatim trace from the first F2 write onward
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let f2Seen = false;
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let restartsAtClm = -1; // restartCount at the moment clm_load goes out
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const funcHist = [0, 0, 0, 0]; // count of decoded gSPI functions F0..F3
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const cmdCounts = new Map<string, number>();
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let ledOn = false;
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@ -131,6 +148,7 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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if (ev.kind === 'header') {
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const k = key(ev.cmd);
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cmdCounts.set(k, (cmdCounts.get(k) ?? 0) + 1);
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if (f2Seen && postF2.length < 400) postF2.push(`HDR ${formatCmd(ev.cmd)}`);
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} else if (ev.kind === 'payload') {
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// Histogram of decoded functions + capture EVERY F2 transfer.
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funcHist[ev.cmd.function & 3]++;
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@ -140,7 +158,19 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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if (chip.debugInboundCount() > 0) statusReadsWithPkt++;
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}
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if (ev.cmd.function === 2 && f2Log.length < 60) {
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f2Log.push(`${ev.cmd.write ? 'WR' : 'RD'} F2 a=0x${ev.cmd.address.toString(16)} len=${ev.payload.length || ev.readBytes}`);
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const head = Array.from(ev.payload.slice(0, 32))
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.map((b) => b.toString(16).padStart(2, '0')).join(' ');
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f2Log.push(`${ev.cmd.write ? 'WR' : 'RD'} F2 a=0x${ev.cmd.address.toString(16)} len=${ev.payload.length || ev.readBytes}` +
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(ev.cmd.write ? `\n bytes: ${head}` : ''));
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}
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if (ev.cmd.function === 2 && ev.cmd.write && !f2Seen) { f2Seen = true; restartsAtClm = restartCount; }
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// Once clm_load (first F2 write) goes out, capture EVERYTHING verbatim
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// (no ring) so we can see exactly where the driver stalls afterward.
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if (f2Seen && postF2.length < 400) {
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postF2.push(`${formatCmd(ev.cmd)} rx=${ev.readBytes}` +
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(ev.cmd.write && ev.payload.length > 0 && ev.payload.length < 8
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? ` =0x${((ev.payload[0] | (ev.payload[1] << 8) | (ev.payload[2] << 16) | (ev.payload[3] << 24)) >>> 0).toString(16)}`
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: ''));
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}
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// Skip the ~3500 firmware-block writes (len>=64) AND the backplane
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// window-address writes (0x1000a/b/c) that bracket each block —
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@ -164,6 +194,11 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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.map((b) => b.toString(16).padStart(2, '0')).join(' ');
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trace.push(`<- (${reply.length}B) ${hex}${reply.length > 8 ? ' ...' : ''}`);
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}
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if (f2Seen && postF2.length < 400) {
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const hex = Array.from(reply.slice(0, 16))
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.map((b) => b.toString(16).padStart(2, '0')).join(' ');
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postF2.push(` <- (${reply.length}B) ${hex}${reply.length > 16 ? ' ...' : ''}`);
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}
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}
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}
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}
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@ -171,17 +206,42 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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let rxPulled = 0;
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let restartCount = 0;
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let txPulls = 0;
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let smSteps = 0;
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for (const pio of (sim.rp2040 as any).pio) {
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for (const sm of pio.machines) {
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const tx = sm.txFIFO;
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if (!tx) continue;
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const orig = tx.push.bind(tx);
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// Make the TX FIFO NON-DROPPING by swapping its fixed 4-deep backing
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// for an unbounded queue. rp2040js's FIFO.push silently drops when
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// `used === length` (the DMA outruns the PIO drain on large bursts).
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// Real hardware paces the DMA with DREQ so it never drops; the dropped
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// words corrupt the 260-word F2 IOCTL writes (clm_load, ioctls), which
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// is why no F2 payload ever frames. An unbounded queue retains every
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// word so the PIO drains the complete stream — keeping the sniffer
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// (hooked on push) and the driver's view identical (no phantom reads).
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// Head-pointer queue: pull() is O(1) amortized (NO Array.shift, which is
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// O(n) and turned the whole thing O(n^2) — the firmware download stalled).
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const q: number[] = [];
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let head = 0;
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Object.defineProperty(tx, 'full', { get: () => false, configurable: true });
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Object.defineProperty(tx, 'empty', { get: () => head >= q.length, configurable: true });
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Object.defineProperty(tx, 'itemCount', { get: () => q.length - head, configurable: true });
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tx.peek = () => (head < q.length ? q[head] : 0);
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tx.reset = () => { q.length = 0; head = 0; };
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tx.push = (v: number) => {
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pushCount++;
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rawWords.push(v >>> 0);
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if (rawWords.length > 600) rawWords.splice(0, rawWords.length - 400); // ring
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feedWord(v, sm);
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return orig(v);
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q.push(v >>> 0);
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};
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tx.pull = () => {
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txPulls++;
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if (head >= q.length) return 0;
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const v = q[head++];
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if (head > 8192 && head * 2 > q.length) { q.splice(0, head); head = 0; } // compact
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return v;
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};
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// Reset the sniffer at each transfer boundary: cyw43_spi_transfer
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// calls pio_sm_restart before pushing the count words, so this keeps
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@ -203,8 +263,43 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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};
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}
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}
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// Crank the PIO step-rate. rp2040js runs the PIO on its own setTimeout
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// loop at only 1000 steps/tick (pio.run) while the CPU's execute() burns
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// 1,000,000 instructions/tick — so a CPU tick (~hundreds of ms wall)
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// starves the PIO, which only gets 1000 steps between ticks. With a
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// non-dropping FIFO the PIO must bit-bang every firmware word, making the
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// ~224KB download take 1000x too long. The gSPI PIO runs near the system
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// clock (clkdiv ~1-2), so let it do up to 1M steps/tick, breaking early
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// once all TX FIFOs are drained to avoid spinning when idle.
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if (typeof pio.run === 'function') {
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pio.run = () => {
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for (let i = 0; i < 1_000_000 && !pio.stopped; i++) {
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pio.step();
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if (i >= 2000 && (i & 1023) === 0) {
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let pending = false;
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for (const m of pio.machines) {
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if (m.txFIFO && !m.txFIFO.empty) { pending = true; break; }
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}
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if (!pending) break;
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}
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}
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if (!pio.stopped) pio.runTimer = setTimeout(() => pio.run(), 0);
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};
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}
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}
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// Drive the WL_HOST_WAKE line (GPIO24 on Pico W). The driver's
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// poll_device gates ALL bus access on this pin being high until it has
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// received its first packet (cyw43_ll.c had_successful_packet). Without
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// it, the first IOCTL (clm_load) is sent but the driver then polls
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// forever getting -1 and never reads the response. Active-high.
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let hostWakeHigh = false;
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chip.onHostWake((active: boolean) => {
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hostWakeHigh = active;
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try { (sim.rp2040 as any).gpio[24].setInputValue(active); } catch { /* noop */ }
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});
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void hostWakeHigh;
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// ── raw REPL injection (mirrors test_micropython_pico.mjs) ──
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const cdc = new USBCDC(sim.rp2040.usbCtrl);
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let serial = '';
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};
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let finished = false;
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const deadline = setTimeout(finish, 60_000);
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// Sample the CPU PC between sim ticks to find busy-wait loops (the driver
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// blocks in active(True) with no bus activity, so a PC histogram localizes
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// the stuck loop — DMA wait, TXSTALL wait, or a delay).
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const pcHist = new Map<number, number>();
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const pcSampler = setInterval(() => {
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const pc = ((sim.rp2040 as any).core?.PC ?? 0) >>> 0;
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pcHist.set(pc, (pcHist.get(pc) ?? 0) + 1);
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}, 20);
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const deadline = setTimeout(finish, 70_000);
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function finish() {
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if (finished) return;
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finished = true;
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clearTimeout(deadline);
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clearInterval(pcSampler);
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// Snapshot the PIO/SM state BEFORE stopping — this is the deadlock state.
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let pioState = '';
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try {
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let pi = 0;
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for (const pio of (sim.rp2040 as any).pio) {
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pioState += `PIO${pi} stopped=${pio.stopped} fdebug=0x${(pio.fdebug >>> 0).toString(16)} txStall=0x${(pio.txStall >>> 0).toString(16)}\n`;
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let si = 0;
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for (const sm of pio.machines) {
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const tx = sm.txFIFO;
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pioState += ` SM${si} en=${sm.enabled} waiting=${sm.waiting} waitType=${sm.waitType} ` +
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`pc=${sm.pc ?? '?'} txDepth=${tx ? tx.itemCount : '?'} rxDepth=${sm.rxFIFO ? sm.rxFIFO.itemCount : '?'}\n`;
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si++;
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}
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pi++;
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}
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} catch (e) { pioState = `pioState err: ${String(e)}`; }
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try { sim.stop(); } catch { /* noop */ }
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const polls = [...cmdCounts.entries()].sort((a, b) => b[1] - a[1]).slice(0, 12);
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const report =
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'===== TOP COMMAND COUNTS (poll loops) =====\n' +
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polls.map(([k, n]) => ` ${String(n).padStart(6)} ${k}`).join('\n') + '\n\n' +
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`===== FUNCTION HISTOGRAM F0..F3 = ${funcHist.join(',')} =====\n` +
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`===== initInbound=${initInbound} statusReads=${statusReads} statusReadsWithPkt=${statusReadsWithPkt} finalInbound=${chip.debugInboundCount()} restarts=${restartCount} =====\n\n` +
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`===== initInbound=${initInbound} statusReads=${statusReads} statusReadsWithPkt=${statusReadsWithPkt} finalInbound=${chip.debugInboundCount()} restarts=${restartCount} =====\n` +
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`===== pushCount=${pushCount} txPulls=${txPulls} smSteps=${smSteps} =====\n` +
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`===== IOCTL ${chip.debugIoctlStats()} =====\n` +
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'===== IOCTL SEQUENCE =====\n' + chip.debugIoctlLog().map((s, i) => ` ${i}: ${s}`).join('\n') + '\n' +
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`===== restartsAtClm=${restartsAtClm} restartsFinal=${restartCount} rxPulled=${rxPulled} =====\n` +
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`===== CPU FAULTS faultCount=${faultCount} =====\n` + faultLog.join('\n') + '\n' +
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'===== HOT PCs (busy-wait localization) =====\n' +
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[...pcHist.entries()].sort((a, b) => b[1] - a[1]).slice(0, 12)
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.map(([pc, n]) => ` ${String(n).padStart(6)} PC=0x${pc.toString(16)}`).join('\n') + '\n\n' +
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'===== PIO/SM STATE AT DEADLINE (deadlock) =====\n' + pioState + '\n' +
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'===== F2/IOCTL TRANSFERS (total seen, non-ring) =====\n' +
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`count=${f2Log.length}\n` + f2Log.join('\n') + '\n\n' +
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'===== POST-CLM_LOAD (verbatim from first F2 write) =====\n' + postF2.join('\n') + '\n\n' +
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'===== TRACE TAIL (post-firmware) =====\n' + trace.slice(-120).join('\n') + '\n\n' +
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'===== LAST RAW TX WORDS (hex) — the end of the run =====\n' +
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rawWords.slice(-70).map((w) => w.toString(16).padStart(8, '0')).join(' ') + '\n';
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@ -297,5 +427,5 @@ describe.skipIf(!process.env.CYW43_HARNESS)('Pico W cyw43 boot harness (investig
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console.log('\n===== reachedImport=' + result.reachedImport + ' reachedActive=' + result.reachedActive + ' =====');
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expect(result.trace.length).toBeGreaterThan(0);
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}, 120_000);
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}, 90_000);
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});
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@ -131,12 +131,32 @@ export class Cyw43Emulator {
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private eventMask = new Uint8Array(32); // up to 256 event types
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private inboundEvents: Uint8Array[] = [];
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// ── Debug counters (investigation harness only) ─────────────────
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private _dbgF2Writes = 0; // F2 write transfers received
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private _dbgFramesDecoded = 0; // SDPCM decode succeeded
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private _dbgSdpcmFail = 0; // SDPCM decode returned null
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private _dbgIoctls = 0; // handleIoctl invoked
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private _dbgIoctlFail = 0; // CDC decode returned null
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private _dbgLastIoctl = -1; // last cdc.cmd seen
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private _dbgIoctlLog: string[] = []; // human-readable IOCTL sequence
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debugIoctlStats(): string {
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return `f2w=${this._dbgF2Writes} sdpcmOk=${this._dbgFramesDecoded} ` +
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`sdpcmFail=${this._dbgSdpcmFail} ioctls=${this._dbgIoctls} ` +
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`ioctlFail=${this._dbgIoctlFail} lastCmd=${this._dbgLastIoctl}`;
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}
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debugIoctlLog(): string[] { return this._dbgIoctlLog; }
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// ── Listeners ───────────────────────────────────────────────────
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private ledListeners: Listener<LedEvent>[] = [];
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private scanListeners: Listener<ScanEvent>[] = [];
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private connectListeners: Listener<ConnectEvent>[] = [];
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private disconnectListeners: Listener<DisconnectEvent>[] = [];
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private packetOutListeners: Listener<PacketOutEvent>[] = [];
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// Host-wake (WL_HOST_WAKE / GPIO24) level listeners. The chip drives this
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// pin high when it has a frame for the host; the driver gates poll_device on
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// it until the first packet is received (cyw43_ll.c had_successful_packet).
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private hostWakeListeners: Listener<boolean>[] = [];
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private hostWakeAsserted = false;
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constructor(opts: Cyw43EmulatorOptions = {}) {
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this.now = opts.now ?? (() => Date.now());
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@ -166,6 +186,7 @@ export class Cyw43Emulator {
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}
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this.inboundEvents.push(sdpcm);
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this.f0Regs[F0.INTERRUPT >> 2] |= 0x40;
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this.updateHostWake();
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}
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// ── Listener registration ───────────────────────────────────────
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@ -174,6 +195,23 @@ export class Cyw43Emulator {
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onConnect = (cb: Listener<ConnectEvent>) => this.add(this.connectListeners, cb);
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onDisconnect = (cb: Listener<DisconnectEvent>) => this.add(this.disconnectListeners, cb);
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onPacketOut = (cb: Listener<PacketOutEvent>) => this.add(this.packetOutListeners, cb);
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/** Fires with the WL_HOST_WAKE pin level (true=high) whenever it changes. */
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onHostWake = (cb: Listener<boolean>) => {
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const off = this.add(this.hostWakeListeners, cb);
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cb(this.hostWakeAsserted); // deliver current level on subscribe
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return off;
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};
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/**
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* Recompute the host-wake (GPIO24) level from the inbound-frame queue and
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* notify listeners on a change. Active-high: high while a frame is pending.
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*/
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private updateHostWake(): void {
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const want = this.inboundEvents.length > 0;
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if (want === this.hostWakeAsserted) return;
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this.hostWakeAsserted = want;
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for (const cb of this.hostWakeListeners) cb(want);
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}
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private add<T>(arr: Listener<T>[], cb: Listener<T>): () => void {
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arr.push(cb);
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@ -240,6 +278,27 @@ export class Cyw43Emulator {
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return this.bigEndian ? bswap32(value >>> 0) : swap16(value >>> 0);
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}
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/**
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* Encode an SDPCM frame for an F2 read. The frame rides the SAME byte-swapped
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* DMA-in path as register reads (cyw43_spi_transfer sets channel bswap=true),
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* so every 32-bit word must be run through encodeReadWord. Without this the
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* frame lands byte-reversed in spid_buf: header_length reads back as garbage
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* and the driver dereferences ioctl_header at an unaligned address (crash).
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*/
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private encodeFrameWords(frame: Uint8Array): Uint8Array {
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// F2/SDPCM traffic only happens after the bus switches to 32-bit big-endian;
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// in the 16-bit boot regime (and the unit tests that exercise IOCTLs there)
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// the frame is consumed raw, so pass it through unchanged.
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if (!this.bigEndian) return frame;
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const out = new Uint8Array(frame.length);
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const whole = frame.length & ~3;
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for (let i = 0; i < whole; i += 4) {
|
||||
writeU32LE(out, i, this.encodeReadWord(readU32LE(frame, i)));
|
||||
}
|
||||
for (let i = whole; i < frame.length; i++) out[i] = frame[i]; // tail (gSPI is word-aligned)
|
||||
return out;
|
||||
}
|
||||
|
||||
/** True once the driver has switched the bus to 32-bit big-endian. */
|
||||
isBigEndian(): boolean { return this.bigEndian; }
|
||||
|
||||
|
|
@ -378,8 +437,10 @@ export class Cyw43Emulator {
|
|||
|
||||
private handleF2(cmd: Cyw43Cmd, _payload: Uint8Array, _rxBytes: number): Uint8Array | null {
|
||||
if (cmd.write) {
|
||||
this._dbgF2Writes++;
|
||||
const frame = decodeSdpcm(_payload);
|
||||
if (frame) this.handleHostFrame(frame.channel, frame.payload);
|
||||
if (frame) { this._dbgFramesDecoded++; this.handleHostFrame(frame.channel, frame.payload); }
|
||||
else this._dbgSdpcmFail++;
|
||||
return null;
|
||||
}
|
||||
|
||||
|
|
@ -395,7 +456,8 @@ export class Cyw43Emulator {
|
|||
if (this.inboundEvents.length === 0) {
|
||||
this.f0Regs[F0.INTERRUPT >> 2] &= ~0x40;
|
||||
}
|
||||
return out;
|
||||
this.updateHostWake();
|
||||
return this.encodeFrameWords(out);
|
||||
}
|
||||
|
||||
// ── Host → chip frame dispatch ──────────────────────────────────
|
||||
|
|
@ -418,9 +480,13 @@ export class Cyw43Emulator {
|
|||
// ── IOCTL handler ───────────────────────────────────────────────
|
||||
|
||||
private handleIoctl(cdcBytes: Uint8Array): void {
|
||||
this._dbgIoctls++;
|
||||
const cdc = decodeCdc(cdcBytes);
|
||||
if (!cdc) return;
|
||||
const isGet = (cdc.flags & 0x1) === 0; // bit 0 clear = GET
|
||||
if (!cdc) { this._dbgIoctlFail++; return; }
|
||||
this._dbgLastIoctl = cdc.cmd;
|
||||
// SDPCM_SET is 0x2 (bit 1) in the CDC flags; SDPCM_GET is 0. (cyw43_ll.c)
|
||||
const ioctlKind = cdc.flags & 0x2;
|
||||
const isGet = ioctlKind === 0;
|
||||
const data = cdc.payload;
|
||||
// For SET_VAR/GET_VAR, name is a NUL-terminated string at start of payload.
|
||||
let varName = '';
|
||||
|
|
@ -429,6 +495,9 @@ export class Cyw43Emulator {
|
|||
varName = readCString(data, 0);
|
||||
varOff = varName.length + 1;
|
||||
}
|
||||
if (this._dbgIoctlLog.length < 60) {
|
||||
this._dbgIoctlLog.push(`${isGet ? 'GET' : 'SET'} cmd=${cdc.cmd}${varName ? ' ' + varName : ''} dlen=${data.length} outlen=${cdc.outlen}`);
|
||||
}
|
||||
const reqId = (cdc.flags >>> 16) & 0xffff;
|
||||
let response: Uint8Array<ArrayBufferLike> = new Uint8Array(0);
|
||||
const status = 0;
|
||||
|
|
@ -510,8 +579,8 @@ export class Cyw43Emulator {
|
|||
dv.setUint32(0, cdc.cmd, true);
|
||||
dv.setUint16(4, response.length, true);
|
||||
dv.setUint16(6, 0, true);
|
||||
// Mirror the request-id in the upper 16 bits, set bit 0 to mark "response"
|
||||
dv.setUint32(8, ((reqId & 0xffff) << 16) | (isGet ? 0 : 1), true);
|
||||
// Mirror the request-id in the upper 16 bits and echo the SET/GET kind bit.
|
||||
dv.setUint32(8, ((reqId & 0xffff) << 16) | ioctlKind, true);
|
||||
dv.setUint32(12, status >>> 0, true);
|
||||
replyCdc.set(response, CDC_HEADER_LEN);
|
||||
const sdpcm = encodeSdpcm({
|
||||
|
|
|
|||
Loading…
Reference in New Issue