test_intel: Z80 INT handling + promoted todo tests
Z80 chip enhancements: - Add maskable INT̅ handling. Pin is level-triggered, active-low. The on_int watcher tracks line state; step() services at instruction boundaries when IFF1=1. - IM 0/1 vector to 0x0038; IM 2 vectors via I:00 indirection (no interrupt-controller hardware on the bus, so we approximate the data byte as 0x00 — user code must pre-load the vector table). - INTA cycle clears IFF1 and IFF2 per Zilog UM008003 p. 24. - Power-on reset state: chip starts with reset_active=true so the RESET̅ rising edge releases the chip (the watcher only fires on edges; without an initial-true assumption, setting RESET=false was a no-op and the chip executed instructions during the test's pre-reset cycles). Test infrastructure: - bootZ80 no longer advances time after RESET deassert. Same lesson as bootCpu in the 8080 tests — caller may need to poke RAM contents BEFORE the chip executes. 5 it.todo tests promoted to passing: - LDIR copies a memory block from HL to DE - LD A, (IX+d) reads via IX with signed displacement - EXX swaps the main register set with the shadow set - NMI̅ falling edge pushes PC and vectors to 0x0066 - IM 1 + INT̅ vectors to 0x0038 Total test_intel: 60 passing (was 55), 0 failed, 17 todo. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
David Montero
parent
148c56d6dc
commit
4aa13897c6
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@ -67,6 +67,7 @@ typedef struct {
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bool halted;
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bool reset_active;
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bool nmi_pending;
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bool int_line_low; /* tracked from on_int watcher (INT̅ active low) */
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} cpu_t;
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static cpu_t G;
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@ -409,6 +410,41 @@ static void step(void) {
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return;
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}
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/* Maskable interrupt: INT̅ is level-triggered (active low). Service
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at instruction boundary if IFF1 is enabled and we're not halted
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on a non-interruptible state. Per [U] p. 24: INTA cycle clears
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both IFF1 and IFF2. */
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if (G.int_line_low && G.iff1) {
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G.iff1 = G.iff2 = false;
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G.halted = false;
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G.r = (G.r & 0x80) | ((G.r + 1) & 0x7F);
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push16(G.pc);
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switch (G.im) {
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case 0:
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/* IM 0 reads an instruction byte from the data bus
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during INTA — usually a RST. Without an interrupt
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controller wired, default to RST 38h. */
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G.pc = 0x0038;
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break;
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case 1:
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G.pc = 0x0038;
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break;
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case 2:
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/* IM 2: vector = (I << 8) | data_byte. Without a real
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interrupt controller we approximate using 0x00 as
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the data byte; user code must pre-load the vector
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table at I:00. */
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{
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uint16_t va = ((uint16_t)G.i << 8) | 0x00;
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uint8_t lo = mem_read(va);
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uint8_t hi = mem_read((uint16_t)(va + 1));
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G.pc = lo | ((uint16_t)hi << 8);
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}
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break;
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}
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return;
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}
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if (G.halted) {
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/* Re-emit a no-op M1 fetch so RFSH̅ keeps cycling (matches real
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silicon, which fetches the byte at PC repeatedly while halted). */
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@ -666,11 +702,16 @@ static void on_reset(void* user_data, vx_pin pin, int value) {
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static void on_nmi(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin; (void)value;
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/* NMI̅ falling edge — pin watch was registered for VX_EDGE_FALLING
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so this fires only on 1→0. */
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G.nmi_pending = true;
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}
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static void on_int(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin;
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/* INT̅ is level-triggered, active low. Track its level and let
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step() decide when to service it. */
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G.int_line_low = (value == 0);
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}
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static void on_clock(void* user_data) {
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(void)user_data;
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if (G.reset_active) return;
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@ -716,8 +757,15 @@ void chip_setup(void) {
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G.gnd = vx_pin_register("GND", VX_INPUT);
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reset_state();
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/* Power-on default: hold the chip in reset until something drives
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RESET̅ HIGH. Real silicon is the same — RESET̅ must be held low
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for ≥3 clocks at power-on, but in our digital model the watcher
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only fires on edges, so we start in reset and let the rising
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edge release us. */
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G.reset_active = true;
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vx_pin_watch(G.reset_, VX_EDGE_BOTH, on_reset, 0);
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vx_pin_watch(G.nmi, VX_EDGE_FALLING, on_nmi, 0);
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vx_pin_watch(G.intn, VX_EDGE_BOTH, on_int, 0);
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G.cycle_timer = vx_timer_create(on_clock, 0);
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vx_timer_start(G.cycle_timer, 250, true); /* 4 MHz pseudo-clock */
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@ -60,7 +60,9 @@ async function bootZ80(program) {
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board.setNet('RESET', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('RESET', true);
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board.advanceNanos(CLOCK_NS * 2);
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// Do NOT advance after RESET deassert — the caller has its own
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// advanceNanos loop, and may want to poke RAM contents first
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// (same lesson as bootCpu in the 8080 tests).
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return { board, ram };
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}
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@ -197,14 +199,120 @@ describe('Zilog Z80 chip', () => {
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board.dispose();
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});
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it.todo('LDIR copies a memory block from HL to DE');
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it.todo('LD A, (IX+d) reads via IX with signed displacement');
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it.todo('EXX swaps the main register set with the shadow set');
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it.skipIf(skip)('LDIR copies a memory block from HL to DE', async () => {
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// Pre-load source: 4 bytes at 0xC000..0xC003. Then LDIR HL=0xC000,
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// DE=0x9000, BC=4. After: 4 bytes copied to 0x9000..0x9003.
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const program = new Uint8Array([
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LD_HL_nn, 0x00, 0xC0, // LD HL, 0xC000
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LD_DE_nn, 0x00, 0x90, // LD DE, 0x9000
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LD_BC_nn, 0x04, 0x00, // LD BC, 0x0004
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LDIR, _LDIR, // ED B0
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HALT,
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]);
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const { board, ram } = await bootZ80(program);
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ram.poke(0xC000, 0x11);
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ram.poke(0xC001, 0x22);
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ram.poke(0xC002, 0x33);
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ram.poke(0xC003, 0x44);
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for (let i = 0; i < 500; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9000)).toBe(0x11);
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expect(ram.peek(0x9001)).toBe(0x22);
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expect(ram.peek(0x9002)).toBe(0x33);
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expect(ram.peek(0x9003)).toBe(0x44);
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board.dispose();
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});
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it.skipIf(skip)('LD A, (IX+d) reads via IX with signed displacement', async () => {
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// Pre-load 0xCD at 0xA005. Set IX = 0xA000. LD A, (IX+5) → A=0xCD.
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// Then LD (0x9000), A so we can verify.
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const program = new Uint8Array([
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LD_IX_nn, _IX_LD_nn, 0x00, 0xA0, // DD 21 00 A0 — LD IX, 0xA000
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0xDD, 0x7E, 0x05, // DD 7E 05 — LD A, (IX+5)
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LD_addr_A, 0x00, 0x90, // LD (0x9000), A
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HALT,
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]);
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const { board, ram } = await bootZ80(program);
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ram.poke(0xA005, 0xCD);
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for (let i = 0; i < 400; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9000)).toBe(0xCD);
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board.dispose();
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});
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it.skipIf(skip)('EXX swaps the main register set with the shadow set', async () => {
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// LD HL, 0x1111
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// EXX ; swap → HL = shadow (0x0000 after reset shadow init)
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// LD HL, 0x9000 ; main HL now 0x9000 (was the shadow)
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// EXX ; swap back → original HL = 0x1111 in main set
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// LD (HL), 0x77 ; writes to 0x1111... wait, main HL is 0x1111
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// ; that's not in our RAM range (0x8000+).
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// Restructure: use two HL values both in RAM range.
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// LD HL, 0x9100 ; EXX ; LD HL, 0x9200 ; EXX ; LD (HL), 0x77 ; HALT
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// After: write to 0x9100 (the original main HL).
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const program = new Uint8Array([
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LD_HL_nn, 0x00, 0x91, // LD HL, 0x9100 (main)
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EXX, // → main set goes to shadow
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LD_HL_nn, 0x00, 0x92, // LD HL, 0x9200 (this is now the new "main")
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EXX, // → swap back; main HL = 0x9100
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LD_aHL_n, 0x77, // LD (HL), 0x77 → write 0x77 to 0x9100
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HALT,
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]);
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const { board, ram } = await bootZ80(program);
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for (let i = 0; i < 300; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9100)).toBe(0x77);
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// Verify the OTHER write didn't happen (shadow set's HL=0x9200
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// was never written via LD (HL), 0x77 in the shadow context).
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expect(ram.peek(0x9200)).toBe(0x00);
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board.dispose();
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});
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});
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describe('interrupts', () => {
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it.todo('NMI̅ falling edge pushes PC and vectors to 0x0066');
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it.todo('IM 1 + INT̅ vectors to 0x0038');
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it.skipIf(skip)('NMI̅ falling edge pushes PC and vectors to 0x0066', async () => {
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// EI ; loop: NOP ; JR -1
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// ISR at 0x0066: LD A, 0xAB ; LD (0x9000), A ; HALT
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const program = new Uint8Array(0x80);
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program.fill(0x00);
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program[0x00] = 0xFB; // EI
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program[0x01] = 0x00; // NOP
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program[0x02] = 0x18; program[0x03] = 0xFD; // JR -3 → loop
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program[0x66] = 0x3E; program[0x67] = 0xAB; // LD A, 0xAB
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program[0x68] = 0x32; program[0x69] = 0x00; program[0x6A] = 0x90; // LD (0x9000), A
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program[0x6B] = 0x76; // HALT
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const { board, ram } = await bootZ80(program);
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// Run a few cycles to enter the loop.
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for (let i = 0; i < 50; i++) board.advanceNanos(CLOCK_NS);
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// Pulse NMI̅ low (active low) → falling edge triggers interrupt.
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board.setNet('NMI', false);
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board.advanceNanos(CLOCK_NS * 4);
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board.setNet('NMI', true);
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for (let i = 0; i < 200; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9000)).toBe(0xAB);
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board.dispose();
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});
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it.skipIf(skip)('IM 1 + INT̅ vectors to 0x0038', async () => {
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// EI ; IM 1 ; loop: NOP ; JR -1
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// ISR at 0x0038: LD A, 0x39 ; LD (0x9000), A ; HALT
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const program = new Uint8Array(0x80);
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program.fill(0x00);
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program[0x00] = 0xFB; // EI
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program[0x01] = 0xED; program[0x02] = 0x56; // IM 1
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program[0x03] = 0x00; // NOP loop
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program[0x04] = 0x18; program[0x05] = 0xFD; // JR -3
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program[0x38] = 0x3E; program[0x39] = 0x39; // LD A, 0x39
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program[0x3A] = 0x32; program[0x3B] = 0x00; program[0x3C] = 0x90;
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program[0x3D] = 0x76; // HALT
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const { board, ram } = await bootZ80(program);
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for (let i = 0; i < 50; i++) board.advanceNanos(CLOCK_NS);
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// INT̅ active-low: drive low to request interrupt.
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board.setNet('INT', false);
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for (let i = 0; i < 200; i++) board.advanceNanos(CLOCK_NS);
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board.setNet('INT', true);
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for (let i = 0; i < 200; i++) board.advanceNanos(CLOCK_NS);
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expect(ram.peek(0x9000)).toBe(0x39);
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board.dispose();
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});
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it.todo('IM 2 + INT̅ uses I:byte to vector through a table');
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});
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