test_intel: Intel 8282 octal latch
Companion chip for 8086 minimum-mode boards that demultiplexes AD0..AD15 → A0..A15 under control of ALE. ~80 LOC clean-room from the public Intel 8282/8283 datasheet. Pin contract (20-pin DIP): DI0..7 in, DO0..7 out, STB strobe, OE̅ output enable, VCC, GND. Behaviour: STB=1, OE̅=0 → DO follows DI (transparent) STB falling → latch held while STB=0 OE̅=1 → DO pins released (modelled as VX_INPUT) Tests: 4/4 passing (pin contract, transparent mode, latch hold, output enable). Brings test_intel total to 47 passing. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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David Montero
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/*
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* Intel 8282 octal latch — clean-room implementation as a velxio
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* custom chip.
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*
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* Source: Intel 8282/8283 datasheet (2-page short form, public).
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* Used to demultiplex AD0..AD7 (or AD8..AD15) on 8086 minimum-mode
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* boards under control of ALE.
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*
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* Behaviour:
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* STB=1, OE̅=0 → transparent: DOn tracks DIn
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* STB 1→0 → latch: hold DOn at DIn captured during STB=1
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* OE̅=1 → release DO pins (high-Z; we model as VX_INPUT)
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*
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* Implementation: pin watches on DI0..7 + STB + OE̅. On any change,
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* recompute outputs:
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* - If OE̅=1: release DO pins.
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* - Else if STB=1: drive DOn = DIn (transparent).
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* - Else: drive DOn from the latched register (set at last STB=1).
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*
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* The 8283 (inverting variant) is NOT implemented here — would just
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* be the same logic with DOn = ~DIn.
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*/
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#include "velxio-chip.h"
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#include <stdint.h>
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#include <stdbool.h>
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typedef struct {
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vx_pin di[8];
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vx_pin dout[8];
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vx_pin stb;
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vx_pin oe;
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vx_pin vcc, gnd;
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uint8_t latched; /* held value when STB is low */
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bool driving;
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} chip_t;
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static chip_t G;
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static uint8_t read_di(void) {
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uint8_t v = 0;
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for (int i = 0; i < 8; i++) if (vx_pin_read(G.di[i])) v |= (1u << i);
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return v;
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}
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static void drive_do(uint8_t v) {
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for (int i = 0; i < 8; i++) {
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vx_pin_set_mode(G.dout[i], VX_OUTPUT);
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vx_pin_write(G.dout[i], (v >> i) & 1);
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}
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G.driving = true;
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}
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static void release_do(void) {
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if (!G.driving) return;
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for (int i = 0; i < 8; i++) vx_pin_set_mode(G.dout[i], VX_INPUT);
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G.driving = false;
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}
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static void update(void) {
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int oe_high = vx_pin_read(G.oe);
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int stb_high = vx_pin_read(G.stb);
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if (oe_high) {
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release_do();
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return;
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}
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if (stb_high) {
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/* Transparent: latched value tracks DI continuously while STB
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is high, AND we drive that value on DO. */
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G.latched = read_di();
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drive_do(G.latched);
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} else {
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/* Latched: DO holds whatever was last captured. */
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drive_do(G.latched);
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}
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}
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static void on_pin_change(void* user_data, vx_pin pin, int value) {
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(void)user_data; (void)pin; (void)value;
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update();
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}
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void chip_setup(void) {
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char name[5];
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for (int i = 0; i < 8; i++) {
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name[0]='D'; name[1]='I'; name[2]='0'+i; name[3]=0;
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G.di[i] = vx_pin_register(name, VX_INPUT);
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}
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for (int i = 0; i < 8; i++) {
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name[0]='D'; name[1]='O'; name[2]='0'+i; name[3]=0;
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G.dout[i] = vx_pin_register(name, VX_INPUT);
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}
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G.stb = vx_pin_register("STB", VX_INPUT);
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G.oe = vx_pin_register("OE", VX_INPUT);
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G.vcc = vx_pin_register("VCC", VX_INPUT);
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G.gnd = vx_pin_register("GND", VX_INPUT);
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G.latched = 0;
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G.driving = false;
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for (int i = 0; i < 8; i++) {
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vx_pin_watch(G.di[i], VX_EDGE_BOTH, on_pin_change, 0);
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}
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vx_pin_watch(G.stb, VX_EDGE_BOTH, on_pin_change, 0);
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vx_pin_watch(G.oe, VX_EDGE_BOTH, on_pin_change, 0);
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update();
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}
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@ -0,0 +1,115 @@
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/**
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* Intel 8282 octal latch — TDD spec.
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*
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* The 8282 is the canonical address latch used on 8086 minimum-mode
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* boards to demultiplex AD0..AD15 → A0..A15. ALE from the 8086 drives
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* STB; when ALE pulses high the latch becomes transparent, when ALE
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* falls the address is latched and held while AD becomes the data bus.
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*
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* 20-pin DIP behaviour (per Intel 8282/8283 datasheet):
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* STB=1, OE̅=0 → DOn = DIn (transparent)
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* STB falling, OE̅=0 → DOn = DIn at the moment STB went 0→1→0
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* (latched, held while STB=0)
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* OE̅=1 → DO pins float (we model by switching to VX_INPUT)
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*
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* The 8283 is the inverting variant (DOn = ~DIn). We implement the
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* non-inverting 8282 only.
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*/
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import { describe, it, expect, beforeEach, afterEach } from 'vitest';
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import { BoardHarness } from '../src/BoardHarness.js';
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import { chipWasmExists } from '../src/helpers.js';
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const CHIP = 'latch-8282';
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const skip = !chipWasmExists(CHIP);
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function pinMap() {
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const m = { STB: 'STB', OE: 'OE', VCC: 'VCC', GND: 'GND' };
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for (let i = 0; i < 8; i++) {
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m[`DI${i}`] = `DI${i}`;
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m[`DO${i}`] = `DO${i}`;
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}
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return m;
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}
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function setDI(board, byte) {
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for (let i = 0; i < 8; i++) board.setNet(`DI${i}`, ((byte >> i) & 1) === 1);
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}
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function readDO(board) {
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let v = 0;
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for (let i = 0; i < 8; i++) if (board.getNet(`DO${i}`)) v |= (1 << i);
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return v;
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}
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describe(`${CHIP} chip`, () => {
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let board;
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beforeEach(() => { board = new BoardHarness(); });
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afterEach(() => { board.dispose(); });
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describe('pin contract', () => {
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it.skipIf(skip)('registers all 20 logical pins', async () => {
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await expect(board.addChip(CHIP, pinMap())).resolves.toBeDefined();
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});
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});
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describe('transparent mode', () => {
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it.skipIf(skip)('DO follows DI while STB=1 and OE̅=0', async () => {
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await board.addChip(CHIP, pinMap());
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board.setNet('OE', false);
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board.setNet('STB', true);
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setDI(board, 0xA5);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0xA5);
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setDI(board, 0x3C);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0x3C);
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});
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});
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describe('latch mode', () => {
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it.skipIf(skip)('holds DI value at the moment STB falls', async () => {
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// Real 8282 is "transparent while STB=1, latched when STB=0".
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// The latched value is whatever DI was at the falling edge.
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await board.addChip(CHIP, pinMap());
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board.setNet('OE', false);
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board.setNet('STB', true);
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setDI(board, 0x77);
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board.advanceNanos(20);
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// Drop STB → freeze
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board.setNet('STB', false);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0x77);
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// Change DI; DO should NOT change.
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setDI(board, 0xFF);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0x77);
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// Raise STB → transparent again
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board.setNet('STB', true);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0xFF);
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});
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});
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describe('output enable', () => {
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it.skipIf(skip)('does not drive DO pins when OE̅ is high', async () => {
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await board.addChip(CHIP, pinMap());
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board.setNet('STB', true);
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setDI(board, 0xAA);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0xAA);
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// OE̅ high → 8282 should release outputs. Externally drive DO
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// pins high; 8282 must not pull them back down.
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board.setNet('OE', true);
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board.advanceNanos(20);
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for (let i = 0; i < 8; i++) board.setNet(`DO${i}`, true);
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board.advanceNanos(20);
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expect(readDO(board)).toBe(0xff);
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});
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});
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});
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