test_intel: status docs for completed chip lineup
All 5 retro CPUs (Intel 4004/4040/8080/8086 + Zilog Z80) plus all 3 bus devices (rom-32k, ram-64k, latch-8282) are now implemented. Update top-level matrix and per-chip READMEs to reflect 63/80 tests passing, 0 failed, 17 deferred. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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David Montero
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@ -108,17 +108,19 @@ address and data pins, just like in a real PCB.
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| Folder | Tests | Code | Notes |
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| ------------ | ----- | ----- | ----- |
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| autosearch/ | n/a | n/a | ✅ Intel 4004/4040/8080 + Zilog Z80 manuals + EPROM/SRAM datasheets cited; PDFs under `pdfs/` |
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| autosearch/ | n/a | n/a | ✅ Intel 4004/4040/8080/8086 + Zilog Z80 manuals + 27C256/HM62256/8282 datasheets cited; PDFs under `pdfs/` |
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| harness | ✅ | ✅ | `BoardHarness`, `helpers`, scripts/ — all working |
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| **test_buses/**| ✅ 13 | ✅ | **🎯 13/13 passing**. `rom-32k.c` (~80 LOC) + `ram-64k.c` (~110 LOC, malloc'd to fit 128 KB initial WASM mem). |
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| **test_4004/**| ✅ 11 | ✅ | **🎯 4 passing + 7 todo. ~150 LOC clean-room from Intel MCS-4 manual (Feb 1973).** Deferred: 46-instruction ISA, SRC/CMRAM strobing, I/O instructions. |
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| **test_4040/**| ✅ 5 | ✅ | **🎯 2 passing + 3 todo. ~250 LOC clean-room from Intel MCS-40 manual (Nov 1974).** Deferred: full INT vectoring, BBS, 14 new opcodes' semantics. |
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| **test_buses/**| ✅ 17 | ✅ | **🎯 17/17 passing**. `rom-32k.c` (~80 LOC) + `ram-64k.c` (~110 LOC) + `latch-8282.c` (~80 LOC). |
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| **test_4004/**| ✅ 12 | ✅ | **🎯 9 passing + 3 todo. ~470 LOC clean-room from Intel MCS-4 manual (Feb 1973).** Full 46-instruction ISA implemented. Deferred: LDM/FIM/Busicom integration tests (need fake 4002 RAM for ACC observability). |
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| **test_4040/**| ✅ 5 | ✅ | **🎯 5/5 passing. ~500 LOC clean-room from Intel MCS-40 manual (Nov 1974).** All 14 new opcodes + INT vectoring + BBS + bank-aware register file. |
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| **test_8080/**| ✅ 20 | ✅ | **🎯 18 passing + 2 todo (CPUDIAG integration). ~470 LOC clean-room from Intel 1975/1981 manuals.** |
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| test_8086/ | ✅ 13 | 📋 | Reset to 0xFFFF0, ALE protocol, basic instructions todo |
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| **test_z80/**| ✅ 13 | ✅ | **🎯 6 passing + 7 todo. ~550 LOC clean-room from Zilog UM008003 + Sean Young's "Undocumented Z80 Documented" v0.91.** Deferred: undocumented X/Y flags, MEMPTR, IM 2 vector, NMI exact, ZEXDOC integration. |
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| **test_8086/**| ✅ 13 | ✅ | **🎯 3 passing + 10 todo. ~750 LOC clean-room from Intel iAPX 86,88 User's Manual (Oct 1979).** Bus protocol + reset to 0xFFFF0 + ModR/M decode + ~50 opcodes (MOV/ALU/Jcc/CALL/RET/LOOP/etc.). Deferred: string ops, MUL/DIV, BCD, port I/O, interrupts. |
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| **test_z80/**| ✅ 13 | ✅ | **🎯 11 passing + 2 todo (IM 2 vectoring, ZEXDOC). ~600 LOC clean-room from Zilog UM008003 + Sean Young's "Undocumented Z80 Documented" v0.91.** Full bus + ISA + INT + NMI + LDIR + IX/IY + EXX + IM 0/1/2. Deferred: undocumented X/Y flags, MEMPTR, full DAA, CB-prefix bit ops. |
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Total: **75 tests authored, 43 passing** (8080: 18, rom-32k: 6,
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ram-64k: 7, z80: 6, 4004: 4, 4040: 2), 3 skipping (8086 chip not
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compiled yet), 29 todo (deferred integration / extended-spec tests).
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Zero failures. No velxio core source has been modified. Run `npm test`
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from `test/test_intel/` to confirm.
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Total: **80 tests authored, 63 passing** (8080: 18, Z80: 11,
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4004: 9, 4040: 5, 8086: 3, rom-32k: 6, ram-64k: 7, latch-8282: 4),
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0 skipping, 17 todo (deferred integration / extended-spec tests).
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Zero failures. **All 5 retro Intel/Zilog CPUs + all 3 bus device
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chips from the original plan are now implemented and validated.**
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No velxio core source has been modified. Run `npm test` from
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`test/test_intel/` to confirm.
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@ -5,9 +5,55 @@ for the spec.
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## Status
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📋 **Spec only.** Recommended **last chip to implement** — most
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complex bus, biggest ISA. Tackle after 8080 and Z80 prove the
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toolchain.
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✅ **Implemented (minimum-mode baseline).** 3/13 active tests pass;
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10 are `it.todo` deferred. ~750 LOC clean-room in `8086.c` compiled
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to `fixtures/8086.wasm`.
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Validated against:
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- Intel 8086 Family User's Manual, October 1979 (PDF at
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`autosearch/pdfs/iapx_86_88_users_manual.pdf`)
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- Cross-checked against 8086tiny (MIT, Adrian Cable),
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MartyPC (MIT, dbalsom — hardware-validated 99.9997% on
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SingleStepTests 8088 V2), YJDoc2/8086-Emulator (Apache+MIT)
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What works:
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- 40-pin minimum-mode contract (AD0..AD15, A16..A19, ALE, RD, WR,
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M/IO, DT/R̅, DEN̅, BHE̅, INTR, NMI, INTA̅, RESET, READY, TEST̅, CLK,
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HOLD, HLDA, MN/MX̅, VCC, GND).
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- Reset state per [I86] PDF p.51: CS=0xFFFF, IP=0, all other segs=0,
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flags clear with reserved bits canonicalised. First fetch at
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physical address 0xFFFF0 with proper ALE strobe.
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- Bus cycle T1-T4 (instruction-per-tick collapse): drive AD with low
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16 addr, A with high 4, pulse ALE, switch AD to input, assert RD̅
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(or drive data + WR̅ for writes).
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- 20-bit physical addressing: (segment<<4)+offset modulo 1 MB.
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- Register file: AX/BX/CX/DX with byte halves (union), SP/BP/SI/DI,
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IP, CS/DS/ES/SS, FLAGS.
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- ModR/M decode for memory operands (Table 4-10 effective-address
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formulas with default-segment selection).
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- ~50 opcodes: NOP, HLT, MOV reg/imm and r/m forms, MOV sreg, MOV
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AL/AX,[addr]; ADD/OR/ADC/SBB/AND/SUB/XOR/CMP r/m + r and reverse
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+ AL/AX-imm forms; Group 1 (immediate ALU); INC/DEC r16; PUSH/POP
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r16; PUSHF/POPF; CLC/STC/CLI/STI/CLD/STD/CMC; conditional short
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jumps Jcc; JMP near/short/far; CALL near/far; RET near/far +imm;
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LOOP/LOOPE/LOOPNE/JCXZ; Group 5 (INC/DEC/CALL/JMP/PUSH r/m16);
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segment-override prefixes.
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Deferred (10 it.todo tests):
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- String ops (MOVS/CMPS/SCAS/LODS/STOS) with REP/REPE/REPNE prefix.
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- MUL/DIV/IMUL/IDIV with their per-flag undefined-ness.
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- BCD adjust (DAA/DAS/AAA/AAS/AAM/AAD).
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- Port I/O instructions (IN/OUT).
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- Hardware interrupts (NMI vector 2; INTR + INTA cycle reading the
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vector byte from the data bus).
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- Maximum-mode bus protocol with QS0/QS1, S0..S2 status pins.
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- Cycle-accurate prefetch queue.
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- Undocumented opcodes (POP CS at 0x0F, SALC at 0xD6 — original
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8086 only).
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Test infrastructure for the multiplexed AD bus + ALE-driven 8282
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demux is also pending — the ISA tests need a fake-8086-ROM helper
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that snapshots AD on ALE rising and drives back during RD̅ asserted.
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## Pin contract (40-pin DIP, minimum mode)
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