feat: enhance ESP32 emulation with SYSTIMER and interrupt handling, update GPIO pin mapping for power/GND
David Montero Crespo
parent
fdbc37b69b
commit
220346f220
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@ -308,6 +308,17 @@ def main() -> None: # noqa: C901 (complexity OK for inline worker)
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_init_done.set()
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lib.qemu_main_loop()
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# With -nographic, qemu_init registers the stdio mux chardev which reads
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# from fd 0. If we leave fd 0 as the JSON-command pipe from the parent,
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# QEMU's mux will consume those bytes and forward them to UART0 RX,
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# corrupting user-sent serial data. Redirect fd 0 to /dev/null before
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# qemu_init runs so the mux gets EOF and leaves our command pipe alone.
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# Save the original pipe fd for the command loop below.
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_orig_stdin_fd = os.dup(0)
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_nul = os.open(os.devnull, os.O_RDONLY)
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os.dup2(_nul, 0)
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os.close(_nul)
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qemu_t = threading.Thread(target=_qemu_thread, daemon=True, name=f'qemu-{machine}')
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qemu_t.start()
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@ -341,9 +352,9 @@ def main() -> None: # noqa: C901 (complexity OK for inline worker)
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threading.Thread(target=_ledc_poll_thread, daemon=True, name='ledc-poll').start()
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# ── 8. Command loop (main thread reads stdin) ─────────────────────────────
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# ── 8. Command loop (main thread reads original stdin pipe) ───────────────
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for raw_line in sys.stdin:
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for raw_line in os.fdopen(_orig_stdin_fd, 'r'):
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raw_line = raw_line.strip()
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if not raw_line:
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continue
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@ -499,11 +499,12 @@ export const SimulatorCanvas = () => {
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`[WirePin] component=${component.id} board=${otherEndpoint.componentId}` +
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` kind=${lookupKey} pinName=${otherEndpoint.pinName} → gpioPin=${pin}`
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);
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if (pin !== null) {
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if (pin !== null && pin >= 0) {
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subscribeComponentToPin(component, pin, selfEndpoint.pinName);
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} else {
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} else if (pin === null) {
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console.warn(`[WirePin] Could not resolve pin "${otherEndpoint.pinName}" on ${lookupKey}`);
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}
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// pin === -1 → power/GND pin, skip silently
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}
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});
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}
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@ -40,9 +40,31 @@ const GPIO_W1TC = 0x0C; // GPIO_OUT_W1TC — clear bits (write-only)
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const GPIO_IN = 0x3C; // GPIO_IN_REG — input value (read-only)
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const GPIO_ENABLE = 0x20; // GPIO_ENABLE_REG
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// ── SYSTIMER @ 0x60023000 ────────────────────────────────────────────────────
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// The SYSTIMER runs at 16 MHz (CPU_HZ / 10). FreeRTOS programs TARGET0 to
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// fire every 1 ms (16 000 SYSTIMER ticks = 160 000 CPU cycles) and routes the
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// alarm interrupt to CPU interrupt 1 via the interrupt matrix.
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const SYSTIMER_BASE = 0x60023000;
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const SYSTIMER_SIZE = 0x100;
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// Register offsets (ESP32-C3 TRM)
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const ST_INT_ENA = 0x04; // TARGET0/1/2 enable bits
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const ST_INT_RAW = 0x08; // raw interrupt status
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const ST_INT_CLR = 0x0C; // write-1-to-clear
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const ST_INT_ST = 0x10; // masked status (RAW & ENA)
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const ST_UNIT0_OP = 0x14; // write bit30 to snapshot counter
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const ST_UNIT0_VAL_LO = 0x54; // snapshot value low 32 bits
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const ST_UNIT0_VAL_HI = 0x58; // snapshot value high 32 bits
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// ── Interrupt Controller (no-op passthrough) @ 0x600C5000 ───────────────────
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// FreeRTOS configures source→CPU-int routing here; we handle routing ourselves.
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const INTC_BASE = 0x600C5000;
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const INTC_SIZE = 0x800;
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// ── Clock ───────────────────────────────────────────────────────────────────
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const CPU_HZ = 160_000_000;
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const CYCLES_PER_FRAME = Math.round(CPU_HZ / 60);
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/** CPU cycles per FreeRTOS tick (1 ms at 160 MHz). */
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const CYCLES_PER_TICK = 160_000;
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export class Esp32C3Simulator {
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private core: RiscVCore;
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@ -55,6 +77,10 @@ export class Esp32C3Simulator {
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private gpioOut = 0;
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private gpioIn = 0;
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// SYSTIMER emulation state
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private _stIntEna = 0; // ST_INT_ENA register
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private _stIntRaw = 0; // ST_INT_RAW register (bit0 = TARGET0 fired)
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public pinManager: PinManager;
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public onSerialData: ((ch: string) => void) | null = null;
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public onBaudRateChange: ((baud: number) => void) | null = null;
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@ -93,6 +119,8 @@ export class Esp32C3Simulator {
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this._registerUart0();
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this._registerGpio();
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this._registerSysTimer();
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this._registerIntCtrl();
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this.core.reset(IROM_BASE);
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// Initialize SP to top of DRAM — MUST be after reset() which zeroes all regs
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@ -152,7 +180,7 @@ export class Esp32C3Simulator {
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if (changed & (1 << bit)) {
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const state = !!(this.gpioOut & (1 << bit));
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this.onPinChangeWithTime?.(bit, state, timeMs);
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this.pinManager.setPinState(bit, state);
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this.pinManager.triggerPinChange(bit, state);
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}
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}
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}
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@ -160,6 +188,49 @@ export class Esp32C3Simulator {
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);
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}
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private _registerSysTimer(): void {
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this.core.addMmio(SYSTIMER_BASE, SYSTIMER_SIZE,
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(addr) => {
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const off = addr - SYSTIMER_BASE;
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const wordOff = off & ~3;
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const byteIdx = off & 3;
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let word = 0;
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switch (wordOff) {
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case ST_INT_ENA: word = this._stIntEna; break;
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case ST_INT_RAW: word = this._stIntRaw; break;
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case ST_INT_ST: word = this._stIntRaw & this._stIntEna; break;
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case ST_UNIT0_OP: word = (1 << 29); break; // VALID bit always set
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case ST_UNIT0_VAL_LO: word = (this.core.cycles / 10) >>> 0; break;
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case ST_UNIT0_VAL_HI: word = 0; break;
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default: word = 0; break;
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}
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return (word >> (byteIdx * 8)) & 0xFF;
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},
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(addr, val) => {
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const off = addr - SYSTIMER_BASE;
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const wordOff = off & ~3;
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const shift = (off & 3) * 8;
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switch (wordOff) {
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case ST_INT_ENA:
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this._stIntEna = (this._stIntEna & ~(0xFF << shift)) | ((val & 0xFF) << shift);
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break;
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case ST_INT_CLR:
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this._stIntRaw &= ~((val & 0xFF) << shift);
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break;
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}
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},
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);
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}
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/** Interrupt-controller MMIO — FreeRTOS writes source→CPU-int routing here.
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* We handle routing via direct triggerInterrupt() calls so this is a no-op. */
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private _registerIntCtrl(): void {
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this.core.addMmio(INTC_BASE, INTC_SIZE,
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(_addr) => 0,
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(_addr, _val) => {},
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);
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}
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// ── HEX loading ────────────────────────────────────────────────────────────
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/**
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@ -291,9 +362,11 @@ export class Esp32C3Simulator {
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reset(): void {
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this.stop();
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this.rxFifo = [];
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this.gpioOut = 0;
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this.gpioIn = 0;
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this.rxFifo = [];
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this.gpioOut = 0;
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this.gpioIn = 0;
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this._stIntEna = 0;
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this._stIntRaw = 0;
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this.dram.fill(0);
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this.iram.fill(0);
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this.core.reset(IROM_BASE);
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@ -319,9 +392,24 @@ export class Esp32C3Simulator {
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private _loop(): void {
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if (!this.running) return;
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for (let i = 0; i < CYCLES_PER_FRAME; i++) {
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this.core.step();
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// Execute in 1 ms chunks so FreeRTOS tick interrupts fire at ~1 kHz.
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// Each chunk corresponds to one SYSTIMER TARGET0 period (160 000 CPU cycles
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// at 160 MHz = 16 000 SYSTIMER ticks at 16 MHz).
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let rem = CYCLES_PER_FRAME;
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while (rem > 0) {
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const n = rem < CYCLES_PER_TICK ? rem : CYCLES_PER_TICK;
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for (let i = 0; i < n; i++) {
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this.core.step();
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}
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rem -= n;
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// Raise SYSTIMER TARGET0 alarm → CPU interrupt 1 (FreeRTOS tick).
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// mcause = 0x80000001: bit31=interrupt, bits[4:0]=CPU interrupt number 1.
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this._stIntRaw |= 1;
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this.core.triggerInterrupt(0x80000001);
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}
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this.animFrameId = requestAnimationFrame(() => this._loop());
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}
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}
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@ -8,9 +8,12 @@
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* Memory model: flat Uint8Array, caller supplies base address mappings.
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* MMIO: caller installs read/write hooks at specific address ranges.
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*
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* Machine-mode CSR support:
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* mstatus, mie, mtvec, mscratch, mepc, mcause, mtval, mcycle/cycle
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* MRET, ECALL (cause=11), external interrupt dispatch via triggerInterrupt()
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*
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* Limitations (acceptable for educational emulation):
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* - No privilege levels / CSR side-effects (CSR reads return 0)
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* - No interrupts / exceptions (ECALL/EBREAK are no-ops)
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* - No privilege levels below M-mode
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* - No misalignment exceptions
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* - No RV32A (atomic) or floating-point extensions
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*/
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@ -33,6 +36,24 @@ export class RiscVCore {
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/** CPU cycle counter */
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cycles = 0;
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// ── Machine-mode CSR registers ────────────────────────────────────────────
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/** 0x300 mstatus — bit3=MIE (global enable), bit7=MPIE, bits[12:11]=MPP */
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private mstatus = 0;
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/** 0x304 mie — per-source interrupt enable mask */
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private mie = 0;
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/** 0x305 mtvec — trap-vector base address + mode (bit0=vectored) */
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private mtvec = 0;
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/** 0x340 mscratch — scratch register (used by FreeRTOS context switch) */
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private mscratch = 0;
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/** 0x341 mepc — address of interrupted/excepting instruction */
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private mepc = 0;
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/** 0x342 mcause — trap cause; bit31=interrupt, bits[4:0]=cause number */
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private mcause = 0;
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/** 0x343 mtval — trap value (fault address / instruction bits) */
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private mtval = 0;
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/** Pending async interrupt cause (bit31=1). Null when none pending. */
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pendingInterrupt: number | null = null;
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private readonly mem: Uint8Array;
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private readonly memBase: number;
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private readonly mmioRegions: MmioRegion[] = [];
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@ -55,6 +76,53 @@ export class RiscVCore {
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this.regs.fill(0);
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this.pc = resetVector;
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this.cycles = 0;
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this.mstatus = 0;
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this.mie = 0;
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this.mtvec = 0;
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this.mscratch = 0;
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this.mepc = 0;
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this.mcause = 0;
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this.mtval = 0;
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this.pendingInterrupt = null;
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}
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/**
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* Raise a machine-level interrupt. The cause is stored and will be taken at
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* the next instruction boundary when mstatus.MIE (bit3) is set.
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* Bit31=1 for asynchronous interrupts; bits[4:0] = CPU interrupt number.
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*/
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triggerInterrupt(cause: number): void {
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this.pendingInterrupt = cause >>> 0;
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}
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// ── CSR helpers ─────────────────────────────────────────────────────────
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private readCsr(addr: number): number {
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switch (addr) {
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case 0x300: return this.mstatus;
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case 0x304: return this.mie;
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case 0x305: return this.mtvec;
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case 0x340: return this.mscratch;
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case 0x341: return this.mepc;
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case 0x342: return this.mcause;
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case 0x343: return this.mtval;
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case 0xB00: case 0xC00: return this.cycles >>> 0; // mcycle / cycle (low 32)
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case 0xB80: case 0xC80: return 0; // mcycleh / cycleh
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default: return 0;
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}
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}
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private writeCsr(addr: number, val: number): void {
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switch (addr) {
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case 0x300: this.mstatus = val; break;
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case 0x304: this.mie = val; break;
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case 0x305: this.mtvec = val; break;
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case 0x340: this.mscratch = val; break;
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case 0x341: this.mepc = val; break;
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case 0x342: this.mcause = val; break;
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case 0x343: this.mtval = val; break;
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// cycle counters are read-only; ignore writes
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}
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}
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// ── Memory access helpers ───────────────────────────────────────────────
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@ -309,6 +377,26 @@ export class RiscVCore {
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* for this simple model — real chips have variable latency).
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*/
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step(): number {
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// ── Interrupt check ───────────────────────────────────────────────────
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// Take a pending interrupt if global interrupt enable (mstatus.MIE) is set.
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if (this.pendingInterrupt !== null && (this.mstatus & 0x8)) {
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const cause = this.pendingInterrupt;
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this.pendingInterrupt = null;
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const mieOld = (this.mstatus >> 3) & 1; // current MIE
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this.mstatus = (this.mstatus & ~0x88) // clear MPIE (bit7) and MIE (bit3)
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| (mieOld << 7); // MPIE = old MIE
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this.mepc = this.pc;
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this.mcause = cause;
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const intNum = cause & 0x1f;
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// Vectored mode (mtvec[1:0]==1): PC = base + 4*intNum
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// Direct mode (mtvec[1:0]==0): PC = base
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this.pc = ((this.mtvec & 3) === 1)
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? ((this.mtvec & ~3) >>> 0) + (intNum << 2)
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: (this.mtvec & ~3) >>> 0;
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this.cycles++;
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return 1;
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}
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// RV32C: if bits [1:0] != 0b11, it's a 16-bit compressed instruction
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const half = this.readHalf(this.pc);
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let instr: number;
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@ -461,9 +549,42 @@ export class RiscVCore {
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case 0x0f:
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break;
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// SYSTEM (ECALL, EBREAK, CSR* — treat as no-op)
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case 0x73:
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// SYSTEM — CSR instructions, MRET, ECALL, EBREAK, WFI
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case 0x73: {
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const funct12 = (instr >> 20) & 0xfff;
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if (funct3 === 0) {
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// Privileged instructions (not CSR)
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if (funct12 === 0x302) {
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// MRET — return from machine trap
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const mpie = (this.mstatus >> 7) & 1;
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this.mstatus = (this.mstatus & ~0x8) | (mpie << 3); // MIE = MPIE
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this.mstatus |= (1 << 7); // MPIE = 1
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nextPc = this.mepc >>> 0;
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} else if (funct12 === 0x000) {
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// ECALL — synchronous exception (cause=11 for M-mode)
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// Used by FreeRTOS portYIELD to trigger a context switch.
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const mieOld = (this.mstatus >> 3) & 1;
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this.mstatus = (this.mstatus & ~0x88) | (mieOld << 7);
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this.mepc = this.pc; // points at ecall; trap handler adds +4
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this.mcause = 11; // ecall from M-mode
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nextPc = (this.mtvec & ~3) >>> 0; // always direct for exceptions
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}
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// EBREAK (0x001), WFI (0x105) → no-op (advance PC normally)
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break;
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}
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// CSR instructions (funct3 != 0)
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const csrAddr = funct12;
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const csrOld = this.readCsr(csrAddr);
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const isImm = (funct3 & 4) !== 0; // CSRRWI / CSRRSI / CSRRCI
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const operand = isImm ? rs1 : this.reg(rs1); // zimm (5-bit) or register
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this.setReg(rd, csrOld);
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switch (funct3 & 3) {
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case 1: this.writeCsr(csrAddr, operand); break; // CSRRW/I
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case 2: if (operand !== 0) this.writeCsr(csrAddr, csrOld | operand); break; // CSRRS/I
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case 3: if (operand !== 0) this.writeCsr(csrAddr, csrOld & ~operand); break; // CSRRC/I
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}
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break;
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}
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default:
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// Unknown opcode — skip instruction to avoid infinite loop
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@ -134,6 +134,9 @@ const ESP32_PIN_MAP: Record<string, number> = {
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'GPIO36': 36, 'GPIO39': 39,
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// ADC aliases
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'VP': 36, 'VN': 39,
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// Power / GND — not real GPIOs; mapped to -1 so WirePin skips silently
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'GND': -1, 'GND1': -1, 'GND2': -1,
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'VCC': -1, '3V3': -1, '3V3_OUT': -1, '5V': -1, 'VIN': -1, 'EN': -1,
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};
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/** All known board component IDs in the simulator */
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