| 
					
						
							
								
								FPGA_Main.vi
							
						
					
				 | 
				
					
						
							
							berhasil generate  PWM
						
					
				 | 
				2025-03-22 20:59:33 +07:00 | 
			
		
			
			
			
			
				| 
					
						
							
								
								RT_Main.vi
							
						
					
				 | 
				
					
						
							
							berhasil generate  PWM
						
					
				 | 
				2025-03-22 20:59:33 +07:00 | 
			
		
			
			
			
			
				| 
					
						
							
								
								runtime.aliases
							
						
					
				 | 
				
					
						
							
							berhasil nilai analog pake RT mode
						
					
				 | 
				2025-03-19 22:04:59 +07:00 | 
			
		
			
			
			
			
				| 
					
						
							
								
								runtime.lvlps
							
						
					
				 | 
				
					
						
							
							berhasil nilai analog pake RT mode
						
					
				 | 
				2025-03-19 22:04:59 +07:00 | 
			
		
			
			
			
			
				| 
					
						
							
								
								runtime.lvproj
							
						
					
				 | 
				
					
						
							
							sudah lumayan stable di RT_Main
						
					
				 | 
				2025-03-21 21:54:31 +07:00 |