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Merge branch 'PCA9685' into ADS1115 

# Conflicts:
#	hal/hal-pca9685/pca9685-setPWM.vi
ads1115
Anggoro Dwi 2025-03-18 14:26:12 +07:00
parent 30feb0137b 94f46c294d
commit 4ee87d9bde
6 changed files with 4 additions and 80 deletions
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hal/hal-ads1115/ads1115-getRegister.vi
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hal/hal-ads1115/ads1115-readAnalaog.vi
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hal/hal-ads1115/ads1115-setRegister.vi
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hal/hal-pca9685/pca9685-setPWM.vi
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runtime/FPGA_Main.vi
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runtime/runtime.lvproj
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@ -1726,10 +1726,8 @@ AddOutputFilter chunkFilter
<Item Name="myRIO v1.0 Close.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/common/Instrument Driver Framework/myRIO v1.0/myRIO v1.0 Close.vi"/> <Item Name="myRIO v1.0 Close.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/common/Instrument Driver Framework/myRIO v1.0/myRIO v1.0 Close.vi"/>
<Item Name="LVNumericRepresentation.ctl" Type="VI" URL="/&lt;vilib&gt;/Numeric/LVNumericRepresentation.ctl"/> <Item Name="LVNumericRepresentation.ctl" Type="VI" URL="/&lt;vilib&gt;/Numeric/LVNumericRepresentation.ctl"/>
<Item Name="lvSimController.dll" Type="Document" URL="/&lt;vilib&gt;/rvi/Simulation/lvSimController.dll"/> <Item Name="lvSimController.dll" Type="Document" URL="/&lt;vilib&gt;/rvi/Simulation/lvSimController.dll"/>
</Item> <Item Name="IP SPI&amp;I2C.lvlib" Type="Library" URL="/&lt;vilib&gt;/IEDriver/SPIandI2C/FPGA/Library/IP SPI&amp;I2C.lvlib"/>
<Item Name="_chatReg.vi" Type="VI" URL="../../hal/hal-ads1115/_chatReg.vi"/> <Item Name="Clear Errors.vi" Type="VI" URL="/&lt;vilib&gt;/Utility/error.llb/Clear Errors.vi"/>
<Item Name="NiFpgaLv.dll" Type="Document" URL="NiFpgaLv.dll">
<Property Name="NI.PreserveRelativePath" Type="Bool">true</Property>
</Item> </Item>
</Item> </Item>
<Item Name="Build Specifications" Type="Build"> <Item Name="Build Specifications" Type="Build">
@ -1771,82 +1769,6 @@ AddOutputFilter chunkFilter
<Property Name="TargetName" Type="Str">FPGA Target</Property> <Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref">/Mobile-Robot-K4-001/Chassis/FPGA Target/FPGA_Main.vi</Property> <Property Name="TopLevelVI" Type="Ref">/Mobile-Robot-K4-001/Chassis/FPGA Target/FPGA_Main.vi</Property>
</Item> </Item>
<Item Name="pca9685-setPWM" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
<Property Name="AllowEnableRemoval" Type="Bool">false</Property>
<Property Name="BuildSpecDecription" Type="Str"></Property>
<Property Name="BuildSpecName" Type="Str">pca9685-setPWM</Property>
<Property Name="Comp.BitfileName" Type="Str">runtime_FPGATarget_pca9685-setPWM_X4uwSDZDNqw.lvbitx</Property>
<Property Name="Comp.CustomXilinxParameters" Type="Str"></Property>
<Property Name="Comp.MaxFanout" Type="Int">-1</Property>
<Property Name="Comp.RandomSeed" Type="Bool">false</Property>
<Property Name="Comp.Version.Build" Type="Int">0</Property>
<Property Name="Comp.Version.Fix" Type="Int">0</Property>
<Property Name="Comp.Version.Major" Type="Int">1</Property>
<Property Name="Comp.Version.Minor" Type="Int">0</Property>
<Property Name="Comp.VersionAutoIncrement" Type="Bool">false</Property>
<Property Name="Comp.Vivado.EnableMultiThreading" Type="Bool">true</Property>
<Property Name="Comp.Vivado.OptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PhysOptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PlaceDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RouteDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RunPowerOpt" Type="Bool">false</Property>
<Property Name="Comp.Vivado.Strategy" Type="Str">Default</Property>
<Property Name="Comp.Xilinx.DesignStrategy" Type="Str">balanced</Property>
<Property Name="Comp.Xilinx.MapEffort" Type="Str">default(noTiming)</Property>
<Property Name="Comp.Xilinx.ParEffort" Type="Str">standard</Property>
<Property Name="Comp.Xilinx.SynthEffort" Type="Str">normal</Property>
<Property Name="Comp.Xilinx.SynthGoal" Type="Str">speed</Property>
<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
<Property Name="DestinationDirectory" Type="Path">FPGA Bitfiles</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/D/Documents/_KERJAAN/MobileRobot-Program/runtime/FPGA Bitfiles/runtime_FPGATarget_pca9685-setPWM_X4uwSDZDNqw.lvbitx</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA Bitfiles/runtime_FPGATarget_pca9685-setPWM_X4uwSDZDNqw.lvbitx</Property>
<Property Name="ProjectPath" Type="Path">/D/Documents/_KERJAAN/MobileRobot-Program/runtime/runtime.lvproj</Property>
<Property Name="RelativePath" Type="Bool">true</Property>
<Property Name="RunWhenLoaded" Type="Bool">false</Property>
<Property Name="SupportDownload" Type="Bool">true</Property>
<Property Name="SupportResourceEstimation" Type="Bool">false</Property>
<Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref">/Mobile-Robot-K4-001/Chassis/FPGA Target/HAL/PCA9685/pca9685-setPWM.vi</Property>
</Item>
<Item Name="ads1115-readAnalaog" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
<Property Name="AllowEnableRemoval" Type="Bool">false</Property>
<Property Name="BuildSpecDecription" Type="Str"></Property>
<Property Name="BuildSpecName" Type="Str">ads1115-readAnalaog</Property>
<Property Name="Comp.BitfileName" Type="Str">runtime_FPGATarget_ads1115-readAnal_sKgjv+jI1j8.lvbitx</Property>
<Property Name="Comp.CustomXilinxParameters" Type="Str"></Property>
<Property Name="Comp.MaxFanout" Type="Int">-1</Property>
<Property Name="Comp.RandomSeed" Type="Bool">false</Property>
<Property Name="Comp.Version.Build" Type="Int">0</Property>
<Property Name="Comp.Version.Fix" Type="Int">0</Property>
<Property Name="Comp.Version.Major" Type="Int">1</Property>
<Property Name="Comp.Version.Minor" Type="Int">0</Property>
<Property Name="Comp.VersionAutoIncrement" Type="Bool">false</Property>
<Property Name="Comp.Vivado.EnableMultiThreading" Type="Bool">true</Property>
<Property Name="Comp.Vivado.OptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PhysOptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PlaceDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RouteDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RunPowerOpt" Type="Bool">false</Property>
<Property Name="Comp.Vivado.Strategy" Type="Str">Default</Property>
<Property Name="Comp.Xilinx.DesignStrategy" Type="Str">balanced</Property>
<Property Name="Comp.Xilinx.MapEffort" Type="Str">default(noTiming)</Property>
<Property Name="Comp.Xilinx.ParEffort" Type="Str">standard</Property>
<Property Name="Comp.Xilinx.SynthEffort" Type="Str">normal</Property>
<Property Name="Comp.Xilinx.SynthGoal" Type="Str">speed</Property>
<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
<Property Name="DestinationDirectory" Type="Path">FPGA Bitfiles</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/C/Users/a2nr/Documents/Program/runtime/FPGA Bitfiles/runtime_FPGATarget_ads1115-readAnal_sKgjv+jI1j8.lvbitx</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA Bitfiles/runtime_FPGATarget_ads1115-readAnal_sKgjv+jI1j8.lvbitx</Property>
<Property Name="ProjectPath" Type="Path">/C/Users/a2nr/Documents/Program/runtime/runtime.lvproj</Property>
<Property Name="RelativePath" Type="Bool">true</Property>
<Property Name="RunWhenLoaded" Type="Bool">false</Property>
<Property Name="SupportDownload" Type="Bool">true</Property>
<Property Name="SupportResourceEstimation" Type="Bool">false</Property>
<Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref">/Mobile-Robot-K4-001/Chassis/FPGA Target/HAL/ADS1115/ads1115-readAnalaog.vi</Property>
</Item>
</Item> </Item>
</Item> </Item>
</Item> </Item>
@ -1875,10 +1797,12 @@ AddOutputFilter chunkFilter
<Item Name="IO Config FPGA Reference.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/Resource Manager/typedefs/IO Config FPGA Reference.ctl"/> <Item Name="IO Config FPGA Reference.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/Resource Manager/typedefs/IO Config FPGA Reference.ctl"/>
<Item Name="IO IRQ Channels Enum.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/IRQ/typedefs/IO IRQ Channels Enum.ctl"/> <Item Name="IO IRQ Channels Enum.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/IRQ/typedefs/IO IRQ Channels Enum.ctl"/>
<Item Name="IO Manager.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/IO Manager.vi"/> <Item Name="IO Manager.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/IO Manager.vi"/>
<Item Name="IP SPI&amp;I2C.lvlib" Type="Library" URL="/&lt;vilib&gt;/IEDriver/SPIandI2C/FPGA/Library/IP SPI&amp;I2C.lvlib"/>
<Item Name="IRQ Type.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/IRQ/typedefs/IRQ Type.ctl"/> <Item Name="IRQ Type.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/IRQ/typedefs/IRQ Type.ctl"/>
<Item Name="Is FPGA Ref Available.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/Is FPGA Ref Available.vi"/> <Item Name="Is FPGA Ref Available.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/Is FPGA Ref Available.vi"/>
<Item Name="Lock Mutex.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/Lock Mutex.vi"/> <Item Name="Lock Mutex.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/vis/Lock Mutex.vi"/>
<Item Name="LVNumericRepresentation.ctl" Type="VI" URL="/&lt;vilib&gt;/numeric/LVNumericRepresentation.ctl"/> <Item Name="LVNumericRepresentation.ctl" Type="VI" URL="/&lt;vilib&gt;/numeric/LVNumericRepresentation.ctl"/>
<Item Name="lvSimController.dll" Type="Document" URL="/&lt;vilib&gt;/rvi/Simulation/lvSimController.dll"/>
<Item Name="Mutex Collection.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/typedefs/Mutex Collection.ctl"/> <Item Name="Mutex Collection.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/typedefs/Mutex Collection.ctl"/>
<Item Name="myRIO Generic Hardware Reference.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/typedefs/myRIO Generic Hardware Reference.ctl"/> <Item Name="myRIO Generic Hardware Reference.ctl" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/Utilities/typedefs/myRIO Generic Hardware Reference.ctl"/>
<Item Name="myRIO v1.0 Block Write Resource Manager.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/Resource Manager/vis/myRIO v1.0 Block Write Resource Manager.vi"/> <Item Name="myRIO v1.0 Block Write Resource Manager.vi" Type="VI" URL="/&lt;vilib&gt;/myRIO/Common/Instrument Driver Framework/myRIO v1.0/Resource Manager/vis/myRIO v1.0 Block Write Resource Manager.vi"/>